ARM sees future of IP in Artisan

San Mateo, Calif. — ARM Ltd. last week plunked down nearly a billion dollars for what may someday turn out to be a bargain: the right to reserve a seat at the table for the future of intellectual property.

The Cambridge, England, company's purchase of library vendor Artisan Components Inc. (Sunnyvale, Calif.) gave all the appearances of one of those technology megamergers that analysts love to hate. The price — $913 million, a 42 percent premium over Artisan's Street price and almost 53 times Artisan's latest annual earnings — was viewed as a gamble, at the least, on ARM's part. The deal would merge two companies with very different technologies and distribution channels, both of which have struggled with growth in what is generally seen as a declining market.

But executives from both companies denied the deal was an attempt to recapture growth through acquisition when growth by expansion was unachievable, insisting that this is a strategic acquisition. The merger is a "defining transaction in the IP [intellectual-property] business" that will raise the value of ARM IP and IP in general, said Lucio Lanza, a venture capitalist who serves as Artisan's chairman.

ARM's strength has traditionally been in meeting the needs of architectural designers, providing them with MPU cores to differentiate their designs. In contrast, Artisan's forte has been in understanding the physical layer, building libraries that ensure RTL correlates well to silicon.

As process geometries shrink there is a greater need for that kind of linkage. The merger will allow ARM to ensure that its MPU cores — and now, likely, other cores as well — will be more closely correlated with actual silicon. It will also open up the customer-owned-tooling market, or at least assure customers using foundries that ARM cores are built with Artisan libraries.

Looking ahead?
Thus, ARM may have negotiated with one eye to a future in which competitive CPU core design will be impossible without an intimate relationship among IP developer, library developer and foundry.

"IP without physical understanding is decaying in value," Lanza said. "Bringing in the expertise of the physical layer to ARM is very important for the future of ARM but also for the future of IP in general."

Other hoped-for synergies, such as a move toward a single sales organization, may or may not pan out. "The decision makers for libraries and for CPU IP are usually entirely different," said Carl Schlachte, chief executive officer of CPU IP vendor ARC International plc (San Jose, Calif.). "If I were doing the restructuring there I would probably have two independent sales forces."

In some sense ARM may be anticipating an issue that has not yet emerged for the vast majority of its clients. By the time designs move to 65 nanometers, process experts say, there will be a host of new issues facing library and IP developers. Subwavelength lithography will account for many of the design constraints on cells and, increasingly, on the way cells are packed and interconnected. Thus, having uniform libraries across an entire chip will be vital.

Additional rules, such as pattern sensitivities, spacing rules and area rules, will have to be applied across the boundaries of IP blocks as well. And strategies for dealing with process variations will need to be uniform across a chip if decent yields are to be reached. "ARM cores have got to have high yields at 90 and 65 nm," said industry design consultant Mark Rencher of Pivotal Enterprises (Tempe, Ariz.). "Could you imagine a poor-yielding ARM core contributing to an $xxx million SoC [system-on-chip]? Not a good idea."

Further, as leakage current increases and circuit performance drops, IP blocks will become increasingly dependent on specific advanced features in library cells for both speed and power. A good match between library features and RTL requirements is useful today, but it may be absolutely necessary in the future.

However, MIPS Technologies Inc. CEO John Bourgoin disputed the notion that physical and logical design need to be more tightly coupled below 130 nm. True, he said, some benefit can be derived from a closer working relationship — but there's little need to bring that talent in-house.

"The kinds of things you do in the logical design are, to a degree, technologically dependent [on physical design], but those things are not difficult to know and they tend to come from foundries rather than companies like Artisan and [competitor] Virage [Logic Corp.]," said Bourgoin.

The growing importance of the link between process detail and architectural innovation is illustrated in ARM's recently announced Intelligent Energy Management program. An aggressive attack on energy consumption within the CPU core, IEM takes cues from application and operating software about what hardware resources and how much performance will be needed. Then, hardware automatically turns down clock frequencies and supply voltages to individual blocks. Energy consumption is cut to the minimum necessary to meet the deadlines on current tasks.

The technique cannot be implemented without substantial support from the cell library with which the core is synthesized. Cells must be characterized for variable-voltage operation — a still-unsolved problem. Isolation cells and level translators are necessary so that neighboring blocks can operate at different voltages. There must be latches, memories and sequencers that can take a block in and out of anesthesia as its clock and power levels are being changed, and that can put a block to sleep when it is not being used.

Many of these features require detailed understanding of transistor-level device models, often under conditions not specified by foundries in their process design kits. In short, IEM would not be possible without a cooperating library developer.

"In the past, IP and libraries have been decoupled," said Mark Brass, ARM's business development manager. "Now that independence is breaking down." Indeed, "when you are working at the extremes of performance or power savings, the libraries make a lot of difference," said Artisan's president and CEO, Mark Templeton.

Liam Goudge, director of worldwide business development at ARM, suggested how the link between architecture and libraries might become a new source of revenue. "Imagine whole families of new processor and peripheral IP products, based on different combinations of libraries," Goudge said. Such combinations could potentially carry IP into size, power and performance niches that have not previously been accessible to synthesized IP.

The link between CPU performance and library features may explain the justification for Artisan's high price as well as the genesis of the relationship. "It has been clear for some time that we need a closer link to the libraries," said Jerry Ardizzone, president of U.S. operations for ARM.

Other industry executives were somewhat skeptical of this explanation. "I would be very surprised if ARM didn't already have the technology to do their own libraries if they wished," said Bill Dally, Stanford University professor and manager of a stealth-mode startup. "Pretty much everyone who wants performance has to."

Chris Rowen, president and CEO of CPU IP vendor Tensilica Inc., said that as processes get more difficult the link between libraries and architectures must become stronger. "But that doesn't mean a processor architecture should drive library evolution," he said. "Rather, [it's] the other way around — processors will get better by taking advantage of the interaction between library vendors and the whole design industry." Rowen would not like to see "the Artisan library designers . . . having to pay too much attention to what the ARM CPU designers want."

"A lot depends on whether ARM and Artisan continue to operate independently," said Paul Nixon, president and CEO of Intrinsity Inc. (Austin, Texas).

— Additional reporting by Brian Fuller