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TransEDA Announces PCI All-in-One Verification IP and VN-Control 3.0 for PCI Express, PCI-X and PCI Based Designs
Addresses Customer Demand for Ease of Verifying Multi-Bus Architectures
INTEL DEVELOPER FORUM, San Francisco, Calif., Sept. 7, 2004 - TransEDA, a leader in coverage and ready-to-use verification solutions for electronic designs, today announced the availability of its PCI All-in-One verification IP and its latest VN-Control bus-based system-level test generator release 3.0.
Based on existing production-proven technologies, the PCI All-in-One verification IP accelerates adoption of the new PCI Express interface standard for next-generation designs previously supporting PCI-X or PCI interfaces.
The PCI All-in-One verification IP provides a single, compatible programming interface which enables verification teams to easily reuse their tests on systems containing any combination of PCI Express, PCI-X and PCI buses.
The new version of the VN-Control test generator works with TransEDA's verification IP for PCI Express, PCI-X, PCI, Intel processor buses, or user-created verification IP to speed up debugging and provide greater flexibility for creating bus activity and tests.
About the PCI All-in-One verification IP
The PCI All-in-One verification IP accommodates testing of various system-level configurations such as systems containing PCI Express buses only, a combination of PCI-SIG® standard buses, or a single PCI-SIG standard bus selectively enabled.
Facing the challenges of verifying these different configurations and busses, engineering teams easily create tests with a compatible application programming interface (API) that accesses the bus functional models supplied with the PCI All-in-One verification IP. Greatly reducing engineering effort, these tests can then be reused to verify any of the buses and corresponding interfaces.
To ensure thorough testing, additional APIs are provided for creating tests specific to each bus protocol and different protocol layers. TransEDA's PCI All-in-One and its other verification IP are compatible with the VN-Control test generator and third-party commercial testbench tools.
About the VN-Control test generator
The latest version of the VN-Control test generator creates more sophisticated system-level tests and contains an enhanced debug data display.
Robust design verification requires simulating many real-world conditions.
New functionality in VN-Control enables simulating erroneous transactions and conditions, which in turn thoroughly tests the error-recovery capabilities of the design-under-test.
VN-Control drives this error-injection simulation without the need for user intervention by utilizing new status information from the bus functional models.
In addition, the VN-Control test generator provides a new debugging format that highlights corrupted data, a prelude to system failure.
"The benefits of PCI Express technology appeal to a wide range of manufacturers of applications that include desktop, mobile, server and communications products," said Jim Pappas, Director of Initiatives, Intel Enterprise Platform Group. "TransEDA's announcement of presilicon verification IP and tools reflects the broad adoption of PCI Express throughout the industry and the breadth of tools emerging to support that growth."
"We are responding to our customers' needs to reduce the time spent in verifying increasingly complex systems by creating products that uniquely provide flexibility and enable reuse", said Modesto Casas, Head of Worldwide Marketing at TransEDA. "By leveraging our years of expertise in verification IP for processor and PCI-SIG standard buses, we are able to deliver complete solutions that verify real-world, multiple-bus architectures."
Pricing and Availability
The PCI All-in-One verification IP and the 3.0 version of the VN-Control bus-based system-level test generator are available now. North American and European pricing begins at $15,900 for the PCI All-in-One and $10,600 for VN-Control. TransEDA verification IP for PCI Express, PCI-X 2.0, PCI-X 1.0, PCI, and Intel processor buses are also separately available.
For more information, contact your local representative or visit www.transeda.com.
About TransEDA
TransEDA is a leader in coverage and ready-to-use verification solutions for electronic designs. The company has over ten years of operating experience in the EDA market.
TransEDA provides advanced verification products for simulation platforms including coverability analysis capability, specification coverage and impact analysis, configurable HDL checking, static and property checking, static bus controller coverage, verification IP, bus-based system-level test automation, test suite optimization, and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, and local representatives in China, Korea and Taiwan.
For more information, visit www.transeda.com.
TransEDA, the TransEDA logo, Verification from Concept to Reality, Verification Navigator, VN-Control and PCI All-in-One are registered trademarks of TransEDA Technology Inc.
All other trademarks are the property of their respective holders.
INTEL DEVELOPER FORUM, San Francisco, Calif., Sept. 7, 2004 - TransEDA, a leader in coverage and ready-to-use verification solutions for electronic designs, today announced the availability of its PCI All-in-One verification IP and its latest VN-Control bus-based system-level test generator release 3.0.
Based on existing production-proven technologies, the PCI All-in-One verification IP accelerates adoption of the new PCI Express interface standard for next-generation designs previously supporting PCI-X or PCI interfaces.
The PCI All-in-One verification IP provides a single, compatible programming interface which enables verification teams to easily reuse their tests on systems containing any combination of PCI Express, PCI-X and PCI buses.
The new version of the VN-Control test generator works with TransEDA's verification IP for PCI Express, PCI-X, PCI, Intel processor buses, or user-created verification IP to speed up debugging and provide greater flexibility for creating bus activity and tests.
About the PCI All-in-One verification IP
The PCI All-in-One verification IP accommodates testing of various system-level configurations such as systems containing PCI Express buses only, a combination of PCI-SIG® standard buses, or a single PCI-SIG standard bus selectively enabled.
Facing the challenges of verifying these different configurations and busses, engineering teams easily create tests with a compatible application programming interface (API) that accesses the bus functional models supplied with the PCI All-in-One verification IP. Greatly reducing engineering effort, these tests can then be reused to verify any of the buses and corresponding interfaces.
To ensure thorough testing, additional APIs are provided for creating tests specific to each bus protocol and different protocol layers. TransEDA's PCI All-in-One and its other verification IP are compatible with the VN-Control test generator and third-party commercial testbench tools.
About the VN-Control test generator
The latest version of the VN-Control test generator creates more sophisticated system-level tests and contains an enhanced debug data display.
Robust design verification requires simulating many real-world conditions.
New functionality in VN-Control enables simulating erroneous transactions and conditions, which in turn thoroughly tests the error-recovery capabilities of the design-under-test.
VN-Control drives this error-injection simulation without the need for user intervention by utilizing new status information from the bus functional models.
In addition, the VN-Control test generator provides a new debugging format that highlights corrupted data, a prelude to system failure.
"The benefits of PCI Express technology appeal to a wide range of manufacturers of applications that include desktop, mobile, server and communications products," said Jim Pappas, Director of Initiatives, Intel Enterprise Platform Group. "TransEDA's announcement of presilicon verification IP and tools reflects the broad adoption of PCI Express throughout the industry and the breadth of tools emerging to support that growth."
"We are responding to our customers' needs to reduce the time spent in verifying increasingly complex systems by creating products that uniquely provide flexibility and enable reuse", said Modesto Casas, Head of Worldwide Marketing at TransEDA. "By leveraging our years of expertise in verification IP for processor and PCI-SIG standard buses, we are able to deliver complete solutions that verify real-world, multiple-bus architectures."
Pricing and Availability
The PCI All-in-One verification IP and the 3.0 version of the VN-Control bus-based system-level test generator are available now. North American and European pricing begins at $15,900 for the PCI All-in-One and $10,600 for VN-Control. TransEDA verification IP for PCI Express, PCI-X 2.0, PCI-X 1.0, PCI, and Intel processor buses are also separately available.
For more information, contact your local representative or visit www.transeda.com.
About TransEDA
TransEDA is a leader in coverage and ready-to-use verification solutions for electronic designs. The company has over ten years of operating experience in the EDA market.
TransEDA provides advanced verification products for simulation platforms including coverability analysis capability, specification coverage and impact analysis, configurable HDL checking, static and property checking, static bus controller coverage, verification IP, bus-based system-level test automation, test suite optimization, and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, and local representatives in China, Korea and Taiwan.
For more information, visit www.transeda.com.
TransEDA, the TransEDA logo, Verification from Concept to Reality, Verification Navigator, VN-Control and PCI All-in-One are registered trademarks of TransEDA Technology Inc.
All other trademarks are the property of their respective holders.
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