Cavium Networks Standardizes Upon the MIPS Architecture and Announces cnMIPS Core for Secure Network Services
MOUNTAIN VIEW and SANTA CLARA, Calif , September 13, 2004 -- MIPS Technologies, Inc. (Nasdaq: MIPS) and Cavium Networks today announced that Cavium Networks has standardized upon the industry-standard MIPS64® architecture for the newly announced OCTEON Network Services Processor family, the industry's first single-chip Network Services Processor (NSP). OCTEON Processors target process Layer 3 to Layer 7 networking applications with a standard programming model, and OCTEON NSPs are being designed in to a wide variety of OEM networking equipment including routers, switches and network-edge appliances. Target applications include Firewall, VPN, IDS and Anti-Virus functionality, secure intelligent switches with SSL and content switching, XML switches, intelligent NICs and storage applications.
"For well over a decade, the MIPS architecture has been the technology-of-choice for embedded communication processors because of its inherent performance advantage and broad portfolio of optimized software and tools," said John Bourgoin, president and CEO at MIPS Technologies. "We are excited to see Cavium's highly accomplished microprocessor design team implement an innovative MIPS64-Based core, which will extend the reach of MIPS processors as the de-facto standard for networking applications across all performance ranges."
"Today's processor landscape lacks integrated solutions and architectures suitable for Layer 3 to 7 services, content and security processing at price points required for widespread deployment," said Syed Ali, president and CEO of Cavium Networks. "Our OCTEON Network Services processor family utilizes the industry-standard MIPS architecture in an innovative, highly integrated and scalable manner to address this significant gap. Leveraging the MIPS instruction set architecture and the vast universe of tools and software available will enable users to easily port existing software applications to OCTEON."
About OCTEON Network Services Processor
For more information about the OCTEON Services Processor, please visit: http://www.cavium.com/OCTEON.html.
Webinar and Briefings
Cavium Networks is hosting an OCTEON NSP briefing Webinar on Wednesday, September 22, 2004 at 11 a.m. Pacific Standard Time. To register for the Webinar, please visit: http://www.cavium.com/OCTEON/Webinar.html.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.
About Cavium Networks
Cavium Networks is a worldwide leader in security, network services and content processing semiconductor solutions. Cavium Networks' award-winning NITROX and MIPS64-Based™ OCTEON families of processors and accelerator boards offer flexible, scalable and highly integrated solutions delivering 50Mbps to 10Gbps performance. The company's products are integrated into a wide range of networking equipment that include routers, gateways, network appliances, content switches, wireless LAN access/aggregation points, servers and storage networking devices. Cavium Networks is headquartered in the heart of Silicon Valley in Santa Clara, CA with development centers in Marlboro, MA and Hyderabad, India. For more information, please visit: http://www.cavium.com.
|
Related News
- Cavium Networks Extends MIPS Architecture License
- Realtek Standardizes Upon the MIPS Architecture For High Performance SOCs Targeting the Broadband Market
- IntoPIX Announces Its New Generation Of AES IP-Cores Supporting Higher Bitrate Up To 10/100 Gbps With Optimized Footprint To Secure Network Transmission In AV Applications.
- 64-bit MIPS architecture provides low-power, high-throughput processing for Cavium's new OCTEON III processors
- Altera Supports China Mobile Research Institute in Developing Next-Generation Wireless Networks
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |