ESL tools: Are EDA giants in the game?
EE Times: Latest News ESL tools: Are EDA giants in the game? | |
Richard Goering (09/13/2004 9:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=47204415 | |
Santa Cruz, Calif. — If electronic system-level design tools are the next big EDA wave, it's mostly small vendors and startups that seem to be shooting the curl.
But the biggest companies in design automation say they are not backing away from the tide and are, in fact, building careful ESL strategies to bring the emerging tool category into the mainstream.
ESL is a relatively new term for tools that some EDA vendors have been trying to sell for a decade, with limited success. It generally refers to tools that let designers explore and verify architectures before implementing them in RTL code. In its "2003 EDA Market Trends" report, Gartner Dataquest identifies three ESL markets: design and simulation, behavioral synthesis, and test and verification.
ESL tools accounted for about 4 percent of total EDA revenues in this year's first quarter, according to EDA Consortium statistics. But many observers believe ESL's share will rise dramatically as chip designers turn to 90-nanometer process technologies and confront silicon that can accommodate 100 million gates. At that point, observers believe, pure RTL design will no longer be feasible.
According to Dataquest, the ESL test and verification market will lead the charge, with annual revenues of $270 million by 2007. The ESL design and simulation market is expected to reach $168 million that year. One positive factor in both markets is the general acceptance of SystemC as a standard ESL language for modeling and verification.
The vendors most likely to come to mind today as ESL's biggest promoters are small to midsize EDA providers — companies like CoWare, Summit, Forte, Celoxica, AccelChip and Verisity. Where are Cadence Design Systems, Synopsys and Mentor Graphics, which collectively account for the lion's share of EDA revenues?
"If you look at those three companies, you can see that both Cadence and Synopsys have de-emphasized their ESL efforts," said Gary Smith, chief EDA analyst at Gartner Dataquest. "The message from both companies is that there is no money to be made in the ESL market. Mentor, on the other hand, is putting a major R&D effort into ESL tools." 'Baffling' hesitation
John Cooley, moderator of the E-Mail Synopsys Users Group, said that neither Cadence nor Synopsys is aggressively pushing SystemC tools. "Cadence just bundles what they have and sees what sticks," he said. "Synopsys may be officially pushing SystemC, but unofficially it seems like they've abandoned it. They're not hostile, just indifferent."
"We don't see the big three as our competition in any significant way right now," said Mark Milligan, vice president of marketing at CoWare Inc. "Clearly ESL is a dramatic breakthrough in methodology, and the big guys don't generally pioneer new methodologies."
But Milligan said that Cadence does recognize the value of ESL. Indeed, Cadence recently licensed its Signal Processing Worksystem (SPW) product line to CoWare and made a minority investment in the company, which hired the SPW development team. "Cadence isn't backing away; they chose to create a partnership," Milligan said.
Brett Cline, vice president of marketing at behavioral-synthesis provider Forte Design Systems, also sees a difference among the leading EDA vendors. Cadence is very active in the Open SystemC Initiative (OSCI) and is working with other vendors to "push ESL forward," Cline said, and Mentor is becoming involved in OSCI. But Synopsys, said Cline, is an "odd one. They had SystemC tools and pulled back from that a little bit. I think Synopsys is playing more in the back end."
Mitch Weaver, general manager of Cadence's systems and functional verification division, insisted that Cadence's commitment to ESL is strong."Contrary to what people might be saying, no way are we backing away from [ESL]," he said. "In fact, we're investing in it significantly."
Weaver said the ESL market has four components: verification, which is where most of the money is today; behavioral synthesis; silicon intellectual property (IP) modeled at the transaction level; and "design aggregation and exploration," with tools that let users evaluate architectural trade-offs and partition hardware and software.
In this last category, Cadence last year chose to partner with CoWare, leading some to conclude that Cadence was giving up on ESL. But Weaver said Cadence simply decided to ally with the market leader in design aggregation and exploration. The result, he said, has been impressive growth in SPW's business.
"The dynamics of market adoption in the design aggregation space are a whole different animal. It's a world of startups and small companies," Weaver said. "CoWare is really good at that, so why not get on the horse that's winning right now and go to market together?"
ESL verification, by contrast, is an area that Cadence is targeting directly. Weaver said Cadence's Incisive verification platform not only has SystemC support but a "very broad and deep transaction-level environment," with analysis, modeling and debugging. The environment is closely connected to Cadence's Palladium accelerator, making it possible to debug software and validate hardware/software interfaces early in the design cycle, Weaver said.
"Cadence has the perfect channel for ESL verification," Weaver said. He asserted that Incisive has seen widespread customer adoption, especially in Europe and Japan, and that "thousands" of users are now employing SystemC simulation.
Part of the SystemC transaction-level modeling environment in Incisive came from VCC, an ESL product that Cadence rolled out in the mid-1990s. VCC found only a few customers, and its withdrawal from the marketplace fueled the perception that Cadence was backing away from ESL. But VCC was really more of a "research project" than a mature product offering, Weaver said.
Weaver also revealed that Cadence has a behavioral-synthesis product in the works, based on technology acquired from Get2Chip, which had a product called Architectural Compiler. Instead of placing that product on the market, Cadence took some of the technology and combined it with technology from Cadence Berkeley Labs. The result is "coming out of incubation," Weaver said. "Next year you'll hear some big news from us." Sticking with SystemC
Dataquest's 2003 market trends report states that Synopsys is "backing away" from SystemC and its CoCentric ESL product line. But there is "no truth" to that perception, said Rindert Schutten, director of marketing for system-level solutions at Synopsys Inc.
"A lot of our customers are doing higher-level modeling by creating SystemC models," Schutten said. "This is very well and very strongly supported by Synopsys tool suites."
Synopsys said its ESL products include System Studio, previously called CoCentric Studio, which lets users create and analyze SystemC models. Schutten said the product is being actively sold and has customers all over the world.
Additionally, Schutten noted, SystemC support is built into version 7.2 of the VCS Verilog simulator. That means users can co-simulate with SystemC, Verilog, VHDL, Vera and SystemVerilog in one environment, with support for transaction-level modeling.
Schutten said Synopsys has strengthened its partnership with ARM on SystemC and has joined forces with Virtio to bring that company's system-level modeling technology into System Studio.
But he acknowledged that Synopsys does not offer an automated path from SystemC to RTL. He said Behavioral Compiler and SystemC Compiler were discontinued because customers were unhappy with the quality of results.
Schutten declined to comment on whether Synopsys will re-enter the behavioral-synthesis market but said Synopsys' focus in ESL is verification. "The synthesis aspect, although important, is overshadowed in many designs by modeling and verification," he said. 'Inevitable' deployment
"We think current processes are going to break down as you go to 100 million-gate chips," said Serge Leef, general manager of Mentor's SoC division. "When you're dealing with 200 or 300 pieces of IP, we think the problems are so severe that some level of ESL deployment is going to be inevitable."
In June, Mentor introduced Catapult, a C/C++ behavioral-synthesis tool that had actually been in use for two years beforehand. It will compete with the Cynthesizer from Forte Design Systems — and presumably with Cadence's upcoming behavioral synthesizer.
In hardware/software co-verification, Mentor has offered the Seamless product since 1996. Seamless has been used primarily for high-end wireless systems-on-chip, said Leef, but Mentor is changing the product to enhance its appeal among mainstream designers. Upcoming versions may be more vertically focused, and Mentor is "reconsidering" pricing, Leef said.
For C-based simulation, Mentor's ModelSim offers SystemC support. For platform-based design, Mentor offers Platform Express, which lets users graphically integrate IP into designs while generating testbenches, diagnostics and bus interface logic.
Leef said Mentor has a "performance optimization" product under development that will place computationally intensive software in coprocessors or accelerators. And he said Mentor is preparing a SystemC-based, transaction-level modeling product that's expected to go to early customers this year.
"We're hoping this market develops, and we feel the driver will be the sheer availability of silicon real estate," he said.
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