Indian design house rolls IP verification suite

The company's nVS family includes verification IP for PCI Express, PCI-X versions 1.0 and 2.0, PCMCIA, IEEE 1284 and a UART. These products include bus-functional models, monitors, checkers and test suites, and are available in both encrypted and source-code form in Verilog or VHDL.

Earlier this month, nSys (www.nsysinc.com) rolled out nVS for ASI in Verilog. It includes built-in suites for random, directed and error tests; multiple instantiations for creating complex verification environments; error injection and detection; and an ability to drive bus traffic as an ASI requester. It was validated using the Intel ASI bus-functional model, nSys said.

Behind the nSys IP offerings are 25 engineers in New Delhi. The company's Fremont office is run by Ram Gopalan, director of U.S. operations, a founder of reconfigurable processor startup Cognigine Corp. Gopalan said he's working with several Indian companies that are attempting to bring their expertise to a broader market.

"I recognized an opportunity to do a reverse flow of companies from India," Gopalan said. "I realized that a lot of small groups had specific domain expertise, and required strategic market knowledge to bring them to the U.S. and get established."

nSys was founded several years ago by Atul Bhatia, the company's president. Bhatia worked at DCM Data Products for 20 years in India, where he was an ASIC designer. nSys was founded with the intent of starting an ASIC services company, but that proved to be difficult, Gopalan said.

"Being a services company when you're small is difficult, because customers want size and stability," Gopalan said. "So we got the idea of productizing the verification process. We picked standard I/O areas, especially PCI, since the team had developed a PCI core at DCM."

New-product 'platform'
nSys then developed a "platform" that allowed it to quickly turn out new verification IP products, Gopalan said. Members of the nVS family use the same API, so all that needs to change, with a new offering, are the bus-functional model and the test suites. nSys intends to extend beyond PCI into other interconnect standards.

Two of the company's initial customers were leading EDA software providers Cadence Design Systems Inc. and Synopsys Inc. nSys develops SystemC verification IP for Cadence, and Vera verification IP for Synopsys. Meanwhile, the products that nSys sells on its own are offered in Verilog and VHDL.

Other customers listed at the nSys Web site include AMD, AMCC, Cisco Systems, Dolphin, Genesys, Matrox, Microsoft, Myricom and Pericom.

While others provide verification IP, nSys claims a couple of advantages. One is ease of use. "You can be up and running with our suites in 30 minutes," Gopalan said. "The API has just four commands, and by juggling parameters of those commands, you can pretty much do the complete verification."

Another selling point is the availability of Verilog and VHDL source code. Yet another is the content of the IP offerings, which include a monitor that provides a graphical display and a compliance checker that can point to line numbers in a spec.

Single licenses for nSys' verification IP start at $10,000. An unlimited license can accommodate any number of users for encrypted IP, as well as the option to buy source code. nSys also provides services to back up its verification IP.