English
Jennic to demonstrate Serial RapidIO IP in silicon
Jennic has announced its use of NEC Electronics’ ISSP Structured ASIC technology to develop a test chip for use in RapidIO interoperability tests.
SHEFFIELD, UK –20th September 2004 –Jennic, the system-level Intellectual Property (IP) provider, today announced the test and evaluation of its Serial RapidIO IP core by NEC Electronics. The aim is to provide OEM customers with silicon proven IP that will reduce their development time and the associated risks.
Jennic will incorporate NEC Electronics’ SerDes and a range of test and diagnostic capabilities into their Serial RapidIO IP core, which will then be implemented in a test chip using NEC Electronics’ ISSP Structured ASIC technology. The test chip will then be used to undertake compliance and interoperability testing with products from other members of the RapidIO Trade Association.
"The availability of silicon proven IP is a vital element of the RapidIO ecosystem. The combination of Jennic's system level IP and NEC Electronics’ leading edge ASIC technology provides a compelling solution for OEM customers implementing RapidIO systems," said Iain Scott, Executive Director of the RapidIO Trade Association.
Jennic is an active participant in the RapidIO Trade Association and during the development of this IP has made extensive use of other RapidIO Trade Association sponsored initiatives to ensure standards compliance and compatibility with other vendors solutions: These have included the use of the compliance checklists and functional simulation against the bus functional models that allow behavioural modeling in a system level environment.
Jennic's RapidIO IP product line provides a range of complete, fully integrated RapidIO interface solutions to address a wide range of applications including endpoints and switches. They are based around a common, modular architecture and implement the Physical, Transport and Logical Layer RapidIO standards.
About Jennic
Jennic is a leading provider of Intellectual Property and silicon design services to the broadband communications market. Jennic combines its system expertise, advanced Intellectual Property portfolio and skills in digital, software, mixed-signal and SoC design to deliver performance, cost and time-to-market advantages to its system OEMs and semiconductor customers. Jennic’s Intellectual Property portfolio includes physical layer framers and bus bridges for wide and metro area networks, access network co-processors, line-card connectivity solutions and cellular, low power wireless and data mixed-signal systems.
SHEFFIELD, UK –20th September 2004 –Jennic, the system-level Intellectual Property (IP) provider, today announced the test and evaluation of its Serial RapidIO IP core by NEC Electronics. The aim is to provide OEM customers with silicon proven IP that will reduce their development time and the associated risks.
Jennic will incorporate NEC Electronics’ SerDes and a range of test and diagnostic capabilities into their Serial RapidIO IP core, which will then be implemented in a test chip using NEC Electronics’ ISSP Structured ASIC technology. The test chip will then be used to undertake compliance and interoperability testing with products from other members of the RapidIO Trade Association.
"The availability of silicon proven IP is a vital element of the RapidIO ecosystem. The combination of Jennic's system level IP and NEC Electronics’ leading edge ASIC technology provides a compelling solution for OEM customers implementing RapidIO systems," said Iain Scott, Executive Director of the RapidIO Trade Association.
Jennic is an active participant in the RapidIO Trade Association and during the development of this IP has made extensive use of other RapidIO Trade Association sponsored initiatives to ensure standards compliance and compatibility with other vendors solutions: These have included the use of the compliance checklists and functional simulation against the bus functional models that allow behavioural modeling in a system level environment.
Jennic's RapidIO IP product line provides a range of complete, fully integrated RapidIO interface solutions to address a wide range of applications including endpoints and switches. They are based around a common, modular architecture and implement the Physical, Transport and Logical Layer RapidIO standards.
About Jennic
Jennic is a leading provider of Intellectual Property and silicon design services to the broadband communications market. Jennic combines its system expertise, advanced Intellectual Property portfolio and skills in digital, software, mixed-signal and SoC design to deliver performance, cost and time-to-market advantages to its system OEMs and semiconductor customers. Jennic’s Intellectual Property portfolio includes physical layer framers and bus bridges for wide and metro area networks, access network co-processors, line-card connectivity solutions and cellular, low power wireless and data mixed-signal systems.
|
||||||
Related News
- Jennic validates its Serial RapidIO intellectual property in silicon
- Jennic announces Serial RapidIO to PCI Bridge
- Jennic to provide Serial RapidIO® IP in LSI Logic's RapidChip Platform ASIC Partner Program
- Mercury Computer Systems, Inc. Announces Availability of its Serial RapidIO-Based Silicon IP Core
- Xilinx And Mercury Computer Systems Demonstrate Interoperable Serial RapidIO Solutions On An ATCA Platform
Breaking News
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
|
E-mail This Article | 
|
|
Printer-Friendly Page |