Temento Systems starts activities in Germany and announces the creation of its own office
September 17, 2004 - Montbonnot, France - Temento Systems, SA., the leading technology provider of test and debug tools for FPGA, ICs and Systems today announced the starting of its activities in Germany with the creation of its office based in Berlin.
For this opportunity, Temento Systems will exhibit at FED in Ulm, September 17th/18th, 2004. Temento Systems will especially show its DiaTem Studio® platform. DIATEM Studio® is an integrated family of products that streamlines JTAG test for electronic boards, enables test automation and addresses the engineering and manufacturing test stages. With DIATEM Studio® , test engineers can easily bring-up and debug their boards in less than one day, removing barriers to achieving significant quality and cost benefits downstream.
The high level of performance and flexibility of DiaTem Studio® provides quite unlimited debugging capabilities and boosts the productivity of engineers in charge of test preparation. Unlike other tools, the Netlist analysis is included, providing the user with the test coverage information. But DiaTem Studio® is also extremely powerful as an engineering tool and has been conceived not only to perform interconnect and memory testing in production assemblies, but also to debug designs and prototypes and assemble systems.
<>“This will expand Temento Systems’ distribution network and allow all German Speaking European users to take benefit from DiaTem extended performances immediately” said Rüdiger Hartung, Account Manager for Germany, Austria and North Switzerland. >About Temento Systems
Temento Systems S.A. provides Electronic Design and Test Automation (EDTA) solutions, that enable to test, and to debug electronic products (System on Chip (SoC), FPGAs, Boards, Multi-Chips Modules (MCMs), and Systems). Unlike traditional EDA software providers, Temento Systems offers a broad range of solutions focused on systems design test, starting from the earliest stage of design definition (virtual test), straight through hardware testing (physical test). Temento's solutions are used by product development teams, manufacturing teams, maintenance teams, in major companies, and SME in the semi-conductor, telecommunications, consumer electronics, computer, automotive, and aerospace industries. For more information, visit the Temento web site at http://www.temento.com.
Temento Systems® and DiaTem Studio® are registered trademarks of Temento Systems SA.
|
Related News
- Test and Verification Solutions Limited (TVS) Announces Opening of German Office
- Tessolve to Acquire Germany's Dream Chip Technologies
- Sigasi Redefines Chip Design Creation, Integration, Validation Leveraging Shift-Left Principles
- AI Edge Inference IP Leader Expedera Opens R&D Office in India
- Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition
Breaking News
- Siemens delivers certified and automated design flows for TSMC 3DFabric technologies
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |