ARC Simplifies Processor Configurations

New technology allows user extensions to be created in minutes

SAN JOSE, Calif., October 6, 2004 – ARC International (LSE: ARK), the world leader in configurable CPU/DSP processor cores and subsystems, today announced the latest generation in configurable technology at the Fall Processor Forum in San Jose. ARC's configurable and extendible processors can significantly reduce power and silicon cost and can now be implemented with less time than ever. This new technology, called Extension Interface Automation (EIA), automates the process of extending and configuring processor cores to allow designers the ability to easily implement processors specifically optimized to their applications.

The EIA technology provides a graphical interface for designers to define and test their own proprietary instructions, registers, flags and condition codes. Designers can then create a library of processor components that can be used by the ARChitect™ processor configurator. This automated process allows for a fast learning curve and substantial time savings. EIA was designed to compliment existing, industry-standard design methodologies and supports multiple standard techniques.

EIA also reduces verification risks in the design process through easy generation of cycle-accurate and instruction set simulation models. EIA's pre-verified extension logic and verification environment allows designers to focus on architecture and design, rather than entry and validation.

"Simplifying the process of configuration broadens the market appeal of user-configurable cores,” said Derek Meyer, ARC VP of Marketing. "By automating the process of adding custom extensions to processor cores, designers are able to save valuable time and die size while differentiating their product. For many of our customers, this represents a significant cost savings.”

EIA supports a single point of entry for extensions through the industry standard languages of Verilog or SystemC. Users can enter instructions in the following ways:

• Single language entry using Verilog or SystemC, where all models (HDL, ISS, CAS and Compiler) are then automatically generated from this one source.
• Separate language entry using Verilog or VHDL for the HDL and C++ for the ISS and CAS models

Availability

This latest version of EIA supporting Verilog entry is available now for the ARC 600 and ARC 700 processors. SystemC entry will be available in Q4'04. Additional technical information on EIA is available at www.ARC.com.
About ARC

ARC International is a world leader in low-power, high-performance 32-bit CPU/DSP configurable processor cores, real-time operating systems and development tools for embedded system design. ARC's configurable, extendible cores assist customers in their rapid development of next generation wireless, networking and consumer electronics systems, resulting in exceptionally competitive System-on-Chip products.

ARC International maintains a worldwide presence with corporate offices in San Jose, California, USA and Elstree, UK. The Company has research and development offices located in England and the United States. For more information please visit the ARC website at: www.ARC.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE:ARK).

This press release may include "forward-looking statements" that involve risks and uncertainties. Factors that could cause actual results to differ are discussed in the 'Investment Considerations' section of the Company's web site as well as the listing particulars, dated 28 September 2000, filed with the United Kingdom Listing Authority and the Registrar of Companies in England and Wales. The Company disclaims any obligation to update any forward-looking statements.

ARC, the ARC logo, ARCtangent, ARCangel, ARChitect, ARCform, MQX and MetaWare are trademarks of ARC International. All other brands or product names are the property of their respective holders.