180nm OTP Non Volatile Memory for Standard CMOS Logic Process
Design complexity drives need for ESL
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EE Times: Latest News Design complexity drives need for ESL | |
Brian Bailey (10/08/2004 6:13 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=49900562 | |
In the electronics industry, we are constantly reminded about the need to innovate. Product lifetimes are shrinking at an accelerating pace and the demand for new features can be overwhelming. Design sizes are maintaining their path along Moore's law, which predicts a doubling of design sizes every 18 months. This creates added pressures on the designers, as there has not been a corresponding lengthening of the design cycle. Product lifetimes have actually been shrinking, and hitting the market window becomes increasingly difficult. Much has been done in the industry to try and improve the development process, but one of the fundamental problems is that quality is not considered an integral part of it. Instead, it relies on verification to fix those quality problems later on. Many improvements have been made in the functional verification space, but they have been unable to keep up with the demands placed on them. Some companies have created separate verification teams to tackle the problem, and others have employed huge server farms with hundreds or thousands of simulations performed in parallel. But such approaches do not address the root of the problem; they are merely addressing the symptoms. If the dynamics of the product development cycles remain unchanged, it is possible to derive a new relationship which must hold if a company is to remain a technical leader. Simply stated: The productivity of the development team must double every twelve months.
Data provided by Gartner Dataquest at this year's Design Automation Conference shows that the industry has not been keeping up with these productivity improvements since 2003. To solve this problem, it is time to migrate to the next level of abstraction, the Electronic System Level (ESL), for both design and verification.
Tackling the verification issue first is the easier way to make the transition. While higher abstraction languages are being adopted for testbench generation, there has not been a corresponding increase in the design abstraction against which the testbench is being developed and debugged. This is the place to start.
To succeed with the adoption of ESL for verification, it is also necessary to throw out many of the common misconceptions about today's verification process, which cause too much time to be spent on verifying details of an implementation instead of verifying that the important functionality of the design has been faithfully created.
The industry cannot wait for new EDA tools to come along and fix the problem for them. That is not going to happen, and in many cases is not necessary as existing tools can partially address many of the issues. Companies can achieve the necessary productivity goals by carefully examining and improving their internal processes and making quality a priority from the beginning. Without this, it will become more and more difficult to maintain the doubling of productivity required every year to stay competitive. Brian Bailey is an independent consultant helping companies improve their verification efficiency. He has spent over 20 years creating verification solutions in a number of EDA companies and in recent years has spent most of his time helping the industry understand how and when to adopt new methodologies. He can be reached at brian_bailey@acm.org.
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