Tensilica shows speed

Like ARC Cores and others, Tensilica has touted the virtues of its configurable architecture since its first public disclosures two years ago.

Until now, the company hasn't been able to show that its approach delivers better performance than off-the-shelf processors. But the new scores make the case. On EEMBC's ConsumerMark, for example, a 200-MHz Xtensa design outscored a 550-MHz AMD K6-III by 5.8x. On the telecom benchmark, Xtensa even outperformed TI's 300-MHz C6203 very long-instruction-word DSP by 25 percent. (TI has not yet posted EEMBC scores for its new, 600-MHz C6403 DSP.)

The scores hinge on Tensilica's customizations. The design used for the ConsumerMark score added more than 100,000 gates to the baseline Xtensa design, quintupling its size. But the extra gates delivered a 17x performance boost over the baseline design.

ConsumerMark consists of JPEG compression and decompression, filtering and color-space conversion. In real systems, specialized hardware often handles those tasks. That hardware would have taken less space than the 100,000 gates for the CPU customizations.

Though standard hardware is available for the common functions in this benchmark, Tensilica's design process can be adapted to any function that is needed.

That flexibility leads to slower clocks, because Xtensa processors are synthesized. The benchmarked Xtensa design runs at 200 MHz in 0.18 micron, slower than the K6-III and most similar embedded processors. So, Xtensa's performance shines only when the design has be en customized for the application at hand.

Fortunately, the company's tool suite lets designers quickly create and simulate new configurations and even new instructions. But to achieve the huge performance gains on the EEMBC benchmark required several weeks of effort.

The new data shows Tensilica's configurability can raise performance within a wide range, depending on the task at hand. Designers hoping their application falls near the top of that range will soon be examining Xtensa.