Panel debates value of mixed-signal design tools

Panel debates value of mixed-signal design tools
By Stephan Ohr, EE Times
March 8, 2001 (4:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010306S0088

SANTA CLARA, Calif. — Analog and mixed-signal IC design still represents a major challenge for top-down design flows, according to a panel of semiconductor designers and EDA tool experts assembled last week at the International HDL Conference.

Though analog engineers make up a relatively small proportion of the engineering community, panelists agreed that analog and mixed-signal expertise would be increasingly utilized for communications and consumer circuits. "The consumerization of electronics is driving the use of analog," said Doug Lundin, analog and mixed-signal marketing director for Avanti Corp. "MP3 players, 42-volt automotive battery systems will all be large consumers of analog ICs."

But there was a divergence between what the panel's semiconductor manufacturers said they need and what the tool vendors said they are prepared to deliver — and in how they define the perceived problem. The semiconductor makers found "choke poi nts" in any design flow involving analog, while the tool vendors focused on modeling issues, suggesting that designers' lives would be easier if they learned to model — preferably in some kind of HDL.

Kevin Cameron of National Semiconductor Corp. called attention to "plug and play" issues, and to the apparent assumption by some EDA tool vendors that the analog portions of a circuit would somehow be interchangeable with its digital portions. Having spent much of his career simulating analog and digital circuit elements together, Cameron said he sees promise in hardware description languages like Verilog. But he wished for smoother interfaces and "less of an argument" between Verilog and Spice-level simulations.

The biggest problem for mixed analog-digital design is that their respective tools "don't talk to either other," said John Wright, manager of mixed-signal design at AMI Semiconductor. Especially troublesome are the "interface elements" between the analog and digital sections of a chip, he said. Analog converter blocks frequently require their own power supplies, and hand placement is often required to prevent noise from one section from affecting the other, he said.

Ian Wilson, chief scientist for tool vendor Antrim Design Systems Inc., confirmed that analog design information needs to flow "horizontally" between analog and digital realms, as well as from the top down. But a hard barrier currently stands in the way, said Wilson, who heads Accellera's Verilog-AMS technical standards committee. Top-down design may be the only way to get a jump on designs, he said. "Time-to-market is so compressed, we're experience two Christmases per year," he said.

Tool vendors said they see top-down design flows, model libraries and good model-building tools as essential to new-generation mixed-signal IV/C development. Gary Pratt, technical marketing manager for the analog/mixed-signal product group at Mentor Graphics Corp., called for a form of "model calibration" — a back-and-forth tweaking process that ensures high-level behavioral models don't diverge from lower-level detail models.

"Most people use models, but hate to write them," said Avanti's Lundin. "Engineers don't view modeling as part of what they do."

"Why create a model when circuit designers are not used to doing that?," asked Jonathan Sanders, product engineering director for mixed-signal and physical verification solutions at Cadence Design Systems Inc. Model creation alone can take three-to-five months — time that isn't affordable on a project that might only have three months to make a market window, he said.

Rajit Chandra, a Moscape cofounder and current vice president of technology at Magma Design Automation, said that behavioral and high-level models need more "bottoms-up characterization" to ensure their accuracy and utility. Before it merged with Magma, Moscape built verification software for custom and cell-based designs. At HDLcon, Chandra recommended a partition of large designs into verification blo cks. "Designer should learn to take 'baby steps,' " he said.

But Rob Rutenbar, a professor at Carnegie-Mellon University was conciliatory toward the concerns of both tool and semiconductor makers. "Historically, the tools stink," he acknowledged. But analog circuit synthesis now takes a couple of hours, Rutenbar said, and a new generation of tools can retarget an analog IC to take 78 percent less silicon area and 42 percent less power. "You can do this in a day," he said.