Lattice Introduces New Evaluation Platforms for LatticeEC FPGAs

Standard And Advanced Platforms Allow Quick Evaluation Of Device Performance, Accelerate Development Of Custom Logic And Memory Designs

HILLSBORO, OR - NOVEMBER 15, 2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the immediate availability of two new evaluation platforms for its LatticeEC^TM low-cost FPGAs. These Standard and Advanced Evaluation Platforms will provide users with options for cost effective, easy implementation of system-level logic and memory functions, including support for popular standards such as PCI, DDR, FCRAM and SPI4.2. Each platform provides a general-purpose printed circuit board (PCB) layout built around a LatticeEC FPGA, including a prototyping area, power regulation and standard interface connectors.

"Customer response to our new LatticeEC and LatticeECP^TM devices has been extremely positive," said Stan Kopec, Lattice vice president of corporate marketing. "These low-cost FPGAs dramatically expand Lattice's addressable FPGA market. The availability of these new evaluation platforms, combined with a major upgrade of our design tool software and recently announced IP cores, will encourage even more widespread usage of these new FPGA products."

Standard Evaluation Platform
The LatticeEC Standard Evaluation Platform is a low-cost, flexible PCB designed to allow users to quickly evaluate the performance of LatticeEC FPGAs, or to aid in the development of custom logic and memory designs. This board is designed for basic design evaluation, and is available with either the LatticeEC LFEC6E-4F484C (6K Look-Up Tables/LUTs) or LFEC20E-4F484C device (20K LUTs), an SPI Flash memory for configuration, SMA pads for high-speed signals/clocks, a prototyping area, on-board power control and LEDs for visual feedback.

A free PCI IP Core programming bitstream targeted for this board is scheduled for release later this month to provide an easy means to evaluate Lattice's PCI solution implemented in LatticeEC FPGAs. This design, along with documentation, will be available for download from the Lattice website.

Advanced Evaluation Platform
The LatticeEC Advanced Evaluation Platform is designed for more comprehensive and detailed evaluation or system development. The Advanced Evaluation Platform includes a LatticeEC LFEC20E-5F672C device, a DDR memory interface, SPI4.2 connectors, a PCI interface and on-board FCRAM. SPI Flash memory is included for configuration, as well as SMA connections for external clocking, a prototyping area and on-board power control. The Advanced Evaluation Platform is shipped complete with Lattice's ispDOWNLOAD® cable to support device configuration and a US-/EU-compliant power supply adapter.

Board-compatible PCI, FCRAM, DDR and SPI4.2 IP Core bitstreams are planned for release during the fourth quarter. These IP Cores are designed to allow users to quickly and easily evaluate the LatticeEC device family's superior performance for implementing these common interfaces. More details, and the IP Core bitstreams, will be released on the Lattice web site as soon as they are available.

Users Guides for the Standard and Advanced Evaluation Platforms are available for download from the Lattice web site at: http://www.latticesemi.com/products/devtools/hardware/eval_dev.cfm

Complete Design Solutions - Silicon, Software, IP and Evaluation Platforms
Custom design implementation is easier and more efficient than ever with the comprehensive Lattice ispLEVER® Design Tool, including the new ispTRACY^TM In-System debugging tool, along with recently released intellectual property (IP) cores supporting the LatticeEC device family.

The newly released ispLEVER 4.2 design software, in addition to delivering higher performance, includes a new I/O Assistant for complex I/O placement, Performance Analyst^TM Static Timing Analyzer support, significant floorplanning enhancements and ispTRACY support for the LatticeEC family.

The ispTRACY in-system debugging tool assists the debug of complex circuitry by displaying the logic behavior of internal FPGA device nodes. This is accomplished by capturing internal node states in trace memory implemented in the LatticeEC device's internal block RAMs. The state of these internal nodes can then be written out through the device's JTAG port when user-specified trigger conditions are matched.

Lattice's ispLeverCORE^TM IP supporting the LatticeEC family now includes a wide range of functions such as PCI Target and Master/Target, Gigabit and 10/100 Ethernet MAC, Reed-Solomon and Turbo Encoders and Decoders and other widely used IP solutions.

LatticeEC silicon, ispLeverCORE IP cores, the ispLEVER Design Tool and the new LatticeEC Evaluation Platforms comprise a powerful, efficient and comprehensive approach to system-level design realization and evaluation.

Availability and pricing
The LatticeEC20 Standard and Advanced Evaluation Platforms are available now. List prices begin at $149.

About the LatticeEC FPGA Family
The LatticeEC FPGA device family has been architected to provide the most optimized feature sets, combined with the lowest total solution costs, of any FPGAs. Targeted for general-purpose FPGA applications, the LatticeEC family is a precise and focused response to the market's explosive demand for low-cost, architecturally streamlined logic solutions. Through advanced 130nm silicon technology, an optimized architecture and proprietary circuit design, the new Lattice devices lower total solution costs by up to 30% to 50% compared with existing FPGA solutions, and are expected to broaden the adoption of FPGAs within the $20 billion ASIC marketplace. The LatticeEC family addresses the designer's need to reduce overall solution costs by combining a competitive low-cost FPGA fabric with the capability to interface to low-cost, high-performance DDR 400 memory, and a configuration interface that supports low-cost industry standard SPI memory. In defining its new products to minimize total solution cost, Lattice becomes the first FPGA vendor to provide standard SPI memory configuration.

The first available device, the LatticeEC20, is in production and shipping to customers. The remaining LatticeEC devices are expected to sample in the fourth quarter of 2004, with production release scheduled in the first half of 2005.

About Lattice Semiconductor
Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP™ Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC™), and Programmable Digital Interconnect (GDX™). Lattice also offers industry leading SERDES products. Lattice is “Bringing the Best Together” with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party software suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ISP, GDX, PAC, ispDOWNLOAD, ispLEVER, ispLeverCORE, ispTRACY, LatticeEC, LatticeECP, Performance Analyst and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.