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QualCore Logic Adds Serial ATA, SerDes Cores to Product Portfolio
High-Speed, Flexible Cores Pre-Verified in Silicon
Sunnyvale, Calif., December 7, 2004 –– QualCore Logic, an intellectual property (IP) and full-service, mixed-signal application specific integrated circuit (ASIC) realization company, today said it has added two new intellectual property (IP) cores to its product portfolio.
The first is a digital Serial ATA Host Controller with OCP Interface. The second is high-speed analog dual serializer/deserializer (SerDes) core for SXGA/SXGA+/UXGA application that utilizes a Low Voltage Differential Signaling (LVDS) I/O. This core is used for flat panel displays in laptop computers.
Both cores are intended for use in system-on-chip (SoC) designs. They have taped out and have been implemented in silicon.
Support for Serial ATA with V9201OCP
QualCore Logic’s V9201OCP is a synthesizable IP core compliant with the Serial ATA 1.0a specifications. This IP has a gate count of 60K, excluding memory.
The core is reusable across different on-chip buses with the help of standard bus wrappers. It is configured through a basic Open Core Protocol (OCP) interface, and can be configured to support OCP bus widths of 16, 32 and 64 bits.
Deliverables include: fully synthesizable Verilog Register Transfer Level (RTL) source code and synthesis scripts; documentation; self-checking verification suite; and optional scripts for Static Timing Analysis (STA) and Design For Test (DFT).
Its robust verification suite offers design teams a set of exhaustive test cases, automatic vector checking and log file generation, and automatic generation of the verification suite, as defined by the design team. Added features are Bus Functional Models (BFMs) for Serial ATA 1.0a devices and OCP, Bus Monitor for Serial ATA 1.0a protocol checking, scripts for automated data checking and vector pass/fail/abort reporting.
The core is synchronous and scan friendly. It can attain a fault coverage of 97% with Scan Insertion and ATPG vectors.
QualCore Logic’s SerDes Core
QualCore Logic’s low-power analog 170 MHz SerDes core –– QCSD2-18T transmitter and QCSD3-18T receiver –– is a pre-verified physical layer interface designed for .18-micron technologies. Delivered as two hard macros, it is used for flat panel displays in laptop computers.
The QCSD2-18T transmitter is designed to support single-link transmissions between host and flat-panel display SXGA+ resolutions, and dual link transmissions between host and flat-panel display up to UXGA resolutions. It converts 48 bits of CMOS data into an LVDS data stream, and can be programmed for rising or falling edge clocks through a dedicated pin. The QCSD3-18T receiver includes an Rx section to convert LVDS data streams back into 48 bits of CMOS data with falling or rising edge clock.
In single link using a transmit clock frequency of 135 MHz, data throughput is 472 Mbytes per second. In dual link with a transmit clock frequency of 85 MHz, 48 bits of RGB data is transmitted at an effective rate of 595 Mbps per LVDS channel. Using an 85 MHz clock, data throughput is 595 Mbytes per second.
QCSD3-18T includes a deserializer per link, a clock synthesis unit per link and a demultiplexer block.
Boundary scan logic is included for ease in testing I/Os at the chip or board level. Internal scan is provided in the digital logic.
Availability
Both cores are available now for licensing. Pricing is available upon request.
For more details, visit the QualCore Logic website located at: http://www.qualcorelogic.com. Or, contact its Sales Department at (408) 541-0730, Ext. 205 or sales@qualcorelogic.com
About QualCore Logic
Founded in 1994, QualCore Logic is a leading provider of digital, mixed-signal and analog IP for system-on-chip (SoC) designs. It can take an engineering or register transfer level (RTL) specification to GDSII through final silicon. It operates design and support centers in Sunnyvale, Calif., and Hyderabad, India, with more than 150 design engineers. Corporate headquarters is located at: 1289 Anvilwood Avenue, Sunnyvale, Calif. 94089. Telephone: (408) 541-0730. Facsimile: (408) 541-0731. Email: sales@qualcorelogic.com. Web Site: http://www.qualcorelogic.com
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QualCore Logic acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Sunnyvale, Calif., December 7, 2004 –– QualCore Logic, an intellectual property (IP) and full-service, mixed-signal application specific integrated circuit (ASIC) realization company, today said it has added two new intellectual property (IP) cores to its product portfolio.
The first is a digital Serial ATA Host Controller with OCP Interface. The second is high-speed analog dual serializer/deserializer (SerDes) core for SXGA/SXGA+/UXGA application that utilizes a Low Voltage Differential Signaling (LVDS) I/O. This core is used for flat panel displays in laptop computers.
Both cores are intended for use in system-on-chip (SoC) designs. They have taped out and have been implemented in silicon.
Support for Serial ATA with V9201OCP
QualCore Logic’s V9201OCP is a synthesizable IP core compliant with the Serial ATA 1.0a specifications. This IP has a gate count of 60K, excluding memory.
The core is reusable across different on-chip buses with the help of standard bus wrappers. It is configured through a basic Open Core Protocol (OCP) interface, and can be configured to support OCP bus widths of 16, 32 and 64 bits.
Deliverables include: fully synthesizable Verilog Register Transfer Level (RTL) source code and synthesis scripts; documentation; self-checking verification suite; and optional scripts for Static Timing Analysis (STA) and Design For Test (DFT).
Its robust verification suite offers design teams a set of exhaustive test cases, automatic vector checking and log file generation, and automatic generation of the verification suite, as defined by the design team. Added features are Bus Functional Models (BFMs) for Serial ATA 1.0a devices and OCP, Bus Monitor for Serial ATA 1.0a protocol checking, scripts for automated data checking and vector pass/fail/abort reporting.
The core is synchronous and scan friendly. It can attain a fault coverage of 97% with Scan Insertion and ATPG vectors.
QualCore Logic’s SerDes Core
QualCore Logic’s low-power analog 170 MHz SerDes core –– QCSD2-18T transmitter and QCSD3-18T receiver –– is a pre-verified physical layer interface designed for .18-micron technologies. Delivered as two hard macros, it is used for flat panel displays in laptop computers.
The QCSD2-18T transmitter is designed to support single-link transmissions between host and flat-panel display SXGA+ resolutions, and dual link transmissions between host and flat-panel display up to UXGA resolutions. It converts 48 bits of CMOS data into an LVDS data stream, and can be programmed for rising or falling edge clocks through a dedicated pin. The QCSD3-18T receiver includes an Rx section to convert LVDS data streams back into 48 bits of CMOS data with falling or rising edge clock.
In single link using a transmit clock frequency of 135 MHz, data throughput is 472 Mbytes per second. In dual link with a transmit clock frequency of 85 MHz, 48 bits of RGB data is transmitted at an effective rate of 595 Mbps per LVDS channel. Using an 85 MHz clock, data throughput is 595 Mbytes per second.
QCSD3-18T includes a deserializer per link, a clock synthesis unit per link and a demultiplexer block.
Boundary scan logic is included for ease in testing I/Os at the chip or board level. Internal scan is provided in the digital logic.
Availability
Both cores are available now for licensing. Pricing is available upon request.
For more details, visit the QualCore Logic website located at: http://www.qualcorelogic.com. Or, contact its Sales Department at (408) 541-0730, Ext. 205 or sales@qualcorelogic.com
About QualCore Logic
Founded in 1994, QualCore Logic is a leading provider of digital, mixed-signal and analog IP for system-on-chip (SoC) designs. It can take an engineering or register transfer level (RTL) specification to GDSII through final silicon. It operates design and support centers in Sunnyvale, Calif., and Hyderabad, India, with more than 150 design engineers. Corporate headquarters is located at: 1289 Anvilwood Avenue, Sunnyvale, Calif. 94089. Telephone: (408) 541-0730. Facsimile: (408) 541-0731. Email: sales@qualcorelogic.com. Web Site: http://www.qualcorelogic.com
###
QualCore Logic acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
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