Leading Foundries Spur Widespead Adoption of FSA Mixed-Signal/RF PDK Checklist
SAN JOSE, Calif. (Dec. 7, 2004) – The Fabless Semiconductor Association (FSA), the voice of the global fabless business model, announced today that its Mixed-Signal/RF PDK Checklist, released in March 2004, has been adopted as standard practice into top-tier foundry PDK development workflows and delivered with multiple foundry process design kits (PDKs). The checklist documents the contents of a PDK, which is a set of data files that enable analog circuit and layout designers to efficiently design a semiconductor chip using a set of electronic EDA tools and a selected foundry process.
“We are proud of the work the FSA’s Mixed-Signal/RF Foundry Subcommittee’s PDK working group has done to educate our members about PDK standards and help them initiate work with the checklist,” stated Jodi Shelton, co-founder and executive director of the FSA. “This is just another way that the FSA is providing the industry with new methods to improve the supply chain and enhance the fabless-supplier relationship.”
The working group has monitored and supported the checklist adoption within foundries, EDA tool companies and design service organizations that develop PDKs. The checklist describes simulation models, technology files, design rule files and parameterized cell generators used to design today’s complex mixed-signal and RF ICs. It is both foundry- and EDA-vendor neutral.
“The rapid adoption of the FSA PDK checklist by industry-leading foundries and EDA vendors has reinforced the need for more standardization and infrastructure in the mixed-signal and RF space,” said Paul Kempf, chairman of the FSA Mixed-Signal/RF Foundry Subcommittee and chief marketing and technology officer of Jazz Semiconductor. “The PDK working group was the first working group established within the Mixed-Signal/RF Foundry Subcommittee and has done an excellent job in creating and deploying a standardized document that offers high-level overview of design kit contents.”
Foundries currently adopting the checklist include 1st Silicon, austriamicrosystems, Jazz Semiconductor, PolarFab, Tower Semiconductor, TSMC, UMC and X-FAB. Additionally, EDA vendors and fabless semiconductor members of the FSA’s PDK working group that are also adopting the checklist include Agilent Technologies, Cadence Design Systems, HPL, Mindspeed Technologies, OK Initiative and Silvaco.
“Adoption of the FSA’s PDK Checklist facilitates the clear communication between foundry, fabless customer, EDA vendor, intellectual property (IP) developer and design service providers,” said Ken Brock, chair of the FSA’s PDK working group and vice president of marketing at Silvaco. “The widespread industry adoption of the checklist has motivated the subcommittee to spin off another working group and partner with the FSA modeling subcommittee to deliver the SPICE Model Checklist.”
The FSA Mixed-Signal/RF PDK Checklist and instructions can be downloaded free of charge from the FSA Web site at www.fsa.org/committees/foundry.
About the Fabless Semiconductor Association:
The FSA is the voice of the global fabless business model. Incorporated in 1994, the Association positively impacts the growth and return on invested capital of this business model to enhance the environment for innovation. The FSA provides a platform for meaningful global collaboration between fabless companies and their partners; provides members with timely research and resources; and identifies, debates, and discusses business and technical issues. FSA members include fabless companies and their supply chain and service partners and represent more than 21 countries spanning North America, Asia-Pacific, Europe and the Middle East. www.fsa.org
###
|
Related News
- FSA Introduces Mixed-Signal/RF PDK Checklist Version 2.0
- FSA Releases FSA Mixed-Signal/RF SPICE Model Checklist
- austriamicrosystems is the first to fully comply with Mixed-Signal/RF Process Design KIT guidelines from FSA
- FSA Releases Mixed-Signal/Rf Process Design Kit Guidelines
- Global Semiconductor Alliance Announces Release of Analog/Mixed-Signal/Radio Frequency Process Checklist Version 1.0
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |