Standards panel outlines ESL progress

ESL design has been hinted at and boasted of for over a decade, but tools produced under that banner have either been highly application specific, or have underwhelmed potential customers with their capabilities.

Nonetheless a step-up in abstraction is the accepted wisdom about how the design community can cope with the complexity allowed by the progress of manufacturing in line with Moore's Law. And in the absence of any other ideas the academic and EDA communities have continued to batter their heads against the topic.

The IP-SOC panel included two standards bodies chairman who had some reason to feel that some progress is at last being made.

Alain Clouard, ST program manager in system-level design and chairman of the Open System C Initiative (OSCI) argued that with the hand-off to the IEEE P1666 working group, SystemC is now an accepted and much used standard for the modeling of SoCs at a high level. "The next goal is to foster an ecosystem around the standard," he said.

Ralf von Vignau, director of technology and standardization within Philips Semiconductors, chairs the Spirit consortium. Spirit stands for "Structure for Packaging, Integrating and Re-using IP within Tool flows, which has just promulgated its first standard.

Von Vignau's point was that ESL design within Philips would have to be accompanied by discipline. "It's not a white page for engineers. We will be deploying system-level design using SystemC; the decision has been taken."

Targeted activities will include architectural and performance exploration, software development and mapping to available platforms.

"What is the virtue of standards? They allow ESL to go mainstream. ESL has been around a long time and it has not yet hit the mainstream," said panelist Peter Hardee, vice president of strategic marketing at CoWare Inc. who portrayed ESL as being about to cross a chasm between innovators and pragmatists. "It is very important to innovate first and then standardize what works." With some prompting from the moderator the panel found it hard to disagree with the contention that the Virtual Socket Interface Alliance (VSIA) had largely wasted a great deal of time and energy by trying to take on too much and failing to deliver many usable benefits to chip designers.

While the VSIA now appears to be in turn-around mode a lot of valuable energy was disapated unproductively the moderator, EETimes' Mike Santarini argued.

"There have been a lot of standards efforts and ad hoc groups and they were beginning to learn they are missing the boat. It is a shame because it cast doubt on the standardization process," said von Vignau. "We saw a proliferation of groups; SI2, VSIA, Accellera looking after different niches. We were forced to form Spirit because we didn't believe any of them could sort out the problem."

Joachim Kunkel, vice president of engineering for IP at Synopsys Inc. was eager to emphasize the "tremendous progress" now made by OSCI and Spirit.

But a question from the floor reminded the panelists that many chip and IP developers find inter-standard bodies rivalry off-putting and a reason to defer methodology and purchase decisions; most recently in connection to SystemC versus SystemVerilog.

Another member of the audience asked whether some sort of consensus was building around transaction level modeling as a level of abstraction above RTL and whether this would allow automated methods to develop to take designs from SystemC to VHDL or Verilog.

Synopsys' Kunkel answered by saying that while top-to-bottom synthesis had been largely discredited, the use of "channel" synthesis to define interconnectivity between blocks and where necessary develop RTL patches was being used and the way forward, a point of view endorsed by fellow panelists James Colgan, director of strategic alliances at Sonics Inc.

For ST's Clouard the important thing to stress was that even without automated movement between the transaction level and the RTL, the use of TLM more than pays for itself in terms of speeding up chip design, selecting appropriate blocks and allowing early software development.