ST keynoter sings praises of transaction level modeling

But at the Intellectual Property System on Chip conference Magarshack portrayed that ST travelled a lot further than many of its competitors in terms of taking a holistic view of system-on-chip design and manufacture.

Contained within the keynote, and elsewhere at the conference, were signs that a new level of abstraction somewhere above the register-transfer-level (RTL) is starting to take hold in the industry. Such a move up in abstraction has been long discussed but the number of approaches has proliferated along with the standards bodies.

Magarshack revealed that ST is making some progress in attacking the complexity of System-On-Chip (SoC) design and reducing time to market through the use of transaction level modeling using the SystemC language.

Magarshack also praised the work of the Spirit Consortium (Structure for Packaging, Integrating and Re-using IP within Tool-flows), which published the first version of its standard shortly after Magarshack finished speaking. This was slightly self-congratulatory as Spirit has largely been driven by the Crolles Alliance, which comprises ST, Philips, and Freescale Semiconductor Inc., helped by three of their suppliers; ARM Holdings plc, Mentor Graphics Corp. and Synopys Inc.

Nonetheless Magarshack went on to indicate how the use of high-level descriptions of IP cores or hardware blocks allowed a system description to be put together quickly and modeled effectively, teaching a lot about the system architecture and allowing software development to begin before a line of RTL is written or a block re-used.

He added that standardizing on a TLM (transaction-level modeling) platform should allow third parties to start offering tools around the TLM for such things as tools for performance analysis.

"TLM allows a paradigm shift. It allows us to deliver a prototype [description] to customers before the RTL is frozen."

But Magarschack also pointed out that the proliferation of process technologies, now typically three variants of vanilla logic CMOS per manufacturing node, was creating a burden for IP developers who he said would have to start including threshold voltage variation and back-biasing of transistors within their designs to cope with leakage currents power optimization.

"SoC is at the heart of conflicting trends; upwards towards complexity of hardware and complexity of software down into physical effects." Magarshack listed cross-talk, electro-migration, wire delays annd on-chip variation amongst the physical problems which hound the SoC developer.

The IP industry also had to leave behind the idea that IP is written and then sometime later licensed to a second and third parties. "We can't wait for the IP to be frozen. For us IP is a partnership that takes place every day. In many SoCs half the IP cores are being written at the same time the SoC is being designed."

"Only aa close link between process, design and system-level engineers will yield full specification SoCs," Magarshack concluded.