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Duolog releases SDRAM, DDR2 and NAND Flash sMEM synthesisable memory models to allow functional system validation in a simulation or emulation environment
Dublin, Ireland Jan 5th 2005 -- Duolog Technologies, a leading provider of SoC flow automation intellectual property and design services for the communications semiconductor market, today announced the availability of its SDRAM, DDR2 and NAND Flash memory models to assist functional system verification in a simulation or emulation environment.
The SDRAM and DDR2 memory models are fully cycle accurate with a full command interpreter from initialization sequences to refreshes A core finite state machine implementation supports full memory functionality and facilitates logic validation and debug of command sequences, bank accesses and refresh sequences. a full command interpreter and support configurable memory size and data width.
The models work out of the box on a wide range of emulation environments from custom emulation (Xilinx/Altera) systems to industry standard emulators.
“Any technology which eases the accelleration and emulation of system-level validation is very valuable at the moment.”, commented Dave Murray, “Some of our customers are utilizing these models to do full system-level validation by loading extensive validation programs into the models and running test suites in their target environments. As these models integrate easily into standard simulation and emulation environments, this significantly reduces system verification times and time to market for SoC platforms”.
About Duolog
Duolog Technologies has offices in Dublin & Galway (Ireland) and in Budapest, Hungary. Duolog is a leading supplier of intellectual property, ESL tools and methodology services in the areas of Wired and Wireless Broadband Communications. The company is developing market leading SoC flow design and verification solutions and wireless intellectual property. Duolog also offers hardware and software design services. Further information is available at www.duolog.com
The SDRAM and DDR2 memory models are fully cycle accurate with a full command interpreter from initialization sequences to refreshes A core finite state machine implementation supports full memory functionality and facilitates logic validation and debug of command sequences, bank accesses and refresh sequences. a full command interpreter and support configurable memory size and data width.
The models work out of the box on a wide range of emulation environments from custom emulation (Xilinx/Altera) systems to industry standard emulators.
“Any technology which eases the accelleration and emulation of system-level validation is very valuable at the moment.”, commented Dave Murray, “Some of our customers are utilizing these models to do full system-level validation by loading extensive validation programs into the models and running test suites in their target environments. As these models integrate easily into standard simulation and emulation environments, this significantly reduces system verification times and time to market for SoC platforms”.
About Duolog
Duolog Technologies has offices in Dublin & Galway (Ireland) and in Budapest, Hungary. Duolog is a leading supplier of intellectual property, ESL tools and methodology services in the areas of Wired and Wireless Broadband Communications. The company is developing market leading SoC flow design and verification solutions and wireless intellectual property. Duolog also offers hardware and software design services. Further information is available at www.duolog.com
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