Virage Logic Delivers Faster Time-to-Market, Lower Test Costs, Smaller Area and Better Yield with Third-Generation STAR Memory System(TM)

FREMONT, Calif., Jan 10, 2005 /PRNewswire-FirstCall via COMTEX/ -- A leading provider of semiconductor IP platforms and pioneer in self-test and self-repair embedded memories, Virage Logic Corp. (Nasdaq: VIRL) continues to break new ground with today's announcement of its third-generation Self-Test and Repair (STAR) Memory System(TM). The third-generation STAR Memory System remains the only commercially available integrated embedded memory self-test and self-repair solution. As such, it provides cost-effective on-chip testing and repairing of designs embedding megabits of memories, but adds significant enhancements that result in faster time-to-market, lower test costs, smaller area and better yield for complex System-on-Chip (SoC) designs. The enhancements provide increased intelligence and automation.

"At Ikanos we strongly believe that the challenges presented by designs using deep submicron technologies demand a comprehensive repairable embedded memory solution to ensure high quality and superior yield," said, Joshua Rom, vice president of operations at Ikanos Communications. "We chose Virage Logic's STAR Memory System because of their approach to test and repair as well as extensions to support failure analysis and yield improvement."

Increased Intelligence Improves Yields

In nanometer SoC design, soft errors, memory leakage and the need for high-speed testing are just a few of the challenges plaguing designers. These challenges are compounded by the ever increasing numbers of memory blocks. Virage Logic has added intelligence in both the test and repair architecture and algorithms to meet these challenges. For example, to support high-speed test, critical test functions have been tightly integrated into the memories themselves for extensive and rapid exchange of test patterns and test results between the memories and test engine.

The STAR Memory System's embedded error-correcting-code (ECC) circuitry employs the widely used Single Error Correction, Double Error Detection (SEC- DED) approach to automatically detect and correct soft errors for improved reliability. Since nanometer designs incorporate larger and larger numbers of memories, memory manufacturing defects that impact multiple adjacent memory locations are more prevalent than ever before, and the STAR Memory System has been enhanced to include intelligent test algorithms that detect row and column failures in smaller memories and repair them, ensuring higher yield. Higher leakage currents common at 90-nanometer (nm) and below are addressed by leakage tests to screen out leaking parts and prevent field errors due to reliability issues.

Because SoC designs are becoming increasingly memory-intensive, multiple STAR Memory System instances are often used. To facilitate chip-level integration of multiple STAR Memory instances, Virage Logic has added chip- level IP called the STAR JPC to the STAR Memory System. The STAR JPC acts as a chip-level IP infrastructure hub, vastly reducing routing congestion and resulting in area savings and faster timing closure.

Increased Automation Accelerates Overall Development Schedule

The STAR Memory System also delivers powerful capabilities that enhance design productivity. The STAR Builder is one such productivity booster. The STAR Builder automates the process of STAR Memory System insertion into the functional hierarchy of the SoC design to accelerate the overall product development schedule. By automating the insertion task, the STAR Builder helps manage the complex multi-level design hierarchy and cuts down the overall STAR Memory System implementation time from weeks to days.

"The STAR Memory System's ability to automate the implementation of advanced memory test and repair in our complex, embedded memory-intensive SoCs has greatly simplified the insertion of the memory system into the designs" said Mark Arnold, manager of Agere Systems' Ascot, UK Design Centre. "The STAR Builder also helped us cut design implementation time, which is an important factor in meeting our time-to-market goals."

"At 90-nm and below, memory-intensive SoCs are incredibly complex and therefore bring with them corresponding quality, performance and yield issues" said Jim Ensell, vice president of marketing at Virage Logic. "The significant increased functionality we are delivering in the third-generation STAR Memory System continues to underscore Virage Logic's commitment to helping its customers meet next generation SoC design challenges with advanced integrated self-test and repair technology."

About Virage Logic's STAR Memory System

The STAR Memory System provides the most integrated solution for the cost effective embedding, on-chip testing and repairing of multi-megabit memories. The system includes High-Speed, High-Density or Ultra-Low-Power memories to address a broad range of SoC design requirements. The system consists of one or more STAR and/or ASAP SRAM or ROM Memory blocks, a STAR Processor, a STAR JPC chip-level infrastructure hub to connect multiple STAR Memory System instances, a STAR Fuse Box and a STAR Builder to automate the insertion of the STAR Memory System into the functional hierarchy of the design. Within the same environment, Area, Speed and Power (ASAP) Memory(TM) sub-megabit memories can be tested and used. With customers experiencing yield improvements of up to 250%, the STAR Memory System can potentially save millions of dollars in recovered silicon, substantially reduce test costs, and achieve shorter time-to-volume.

Price and Availability

The third generation STAR Memory System is available today for 180-, 130- and 90-nm memories. STAR Memory System pricing is project-based and depends upon the customer's selection of memories and process technologies.

About Virage Logic

Founded in 1996, Virage Logic Corporation quickly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Virage Logic has evolved to become a global leader in semiconductor IP platforms comprising embedded memory, standard cells, and I/Os primarily for the consumer, communications and networking, handheld and portable, and computer and graphics markets. Virage Logic's highly differentiated product portfolio provides foundries, integrated device manufacturers (IDMs) and fabless customers with key competitive advantages including higher performance, lower power, higher density and optimized yield. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab which is designed to ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.

Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995: Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to products and customers. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to continue to develop new products, Virage Logic's ability to avoid problems related to design or manufacturing of products incorporating its products and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website (www.viragelogic.com) or from the SEC's website (www.sec.gov), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.

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