Embedded software firms ink silicon pacts

TI fires up C64X-based DSPs for 3G wireless run
By Patrick Mannion, EE Times
February 14, 2001 (12:42 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010212S0096

SAN FRANCISCO — Texas Instruments Inc. will officially unleash the first three implementations of its TMS320C64X core on Monday (Feb. 12). The three instantiations of the core, announced last year, target third-generation wireless and broadband infrastructure as well as imaging and video applications. They range in frequency from 400 to 600 MHz, use a 0.12-micron (drawn; 0.13 L_effective) process and extensive on-chip memory. In the case of the wireless infrastructure version, coprocessors handle Viterbi and Turbo code processing.

"At 600 MHz, the new devices will offer the world's highest programmable DSP performance," said Henry Wiechman, marketing manager for TI's C6000 line. "These devices are fully code-compatible with existing C6000 products and offer scalable performance to over 1.1 GHz — and can support multicore designs," he added. Power consumption is rated at 500 milliwatts.

Each version of the processor targets di fferent markets: scientific and military development for the C6414; imaging and video for the C6415; and third-generation (3G) wireless and broadband for the C6416. All use the C64X core with its very long-instruction word architecture and eight functional units that can execute four 16-bit or eight 8-bit multiply-accumulate operations per cycle.

Peripheral support includes a 33-MHz, 32-bit PCI interface and a Utopia II interface for asynchronous transfer mode (ATM) operation. In addition, a 32-bit port on the C6414 aids host connectivity. Up to three multichannel buffered serial ports each support 128 time-division multiplex channels as well as industry-standard audio interfaces, including AC97 and IIS.

The C6416 tops the list in terms of integration. Customized for 3G wireless infrastructure, the device comes with a Viterbi and a Turbo code coprocessor. The Viterbi coprocessor supports over 500 voice channels at 8 kbits/second, with programmable decoder parameters that include constraint length, c ode rate and frame rate.

The Turbo code coprocessor supports 35 data channels at 384 kbits/s, with programmable parameters including mode, rate and frame length.

While the Turbo coprocessor is a key part of TI's plan to maximize core DSP capabilities by off-loading repetitive functions, this approach was questioned by David Baczewski, strategy marketing manager for Motorola's Wireless Infrastructure Systems Division. "Though we pioneered the use of coprocessors, we're careful if we find our customers prefer the flexibility of the programmable approach, so with Turbo codes changing all the time, it doesn't make sense to hardwire it," he said.

Differing approach

Wiechman disagreed. "The coprocessors on the C6416 support the range of Viterbi and Turbo codes that are specified in the third-generation standards. Customers select the particular code that they wish to implement by passing parameters to the coprocessor," he said.

Analog Devices Inc. (Norwood, Mass.) also took issue wi th TI's approach. ADI is targeting the 3G basestation market with its TigerSharc line.

Andrew McCann, marketing manager of ADI's wireless infrastructure group, said, "Thanks to the high prices paid for spectrum worldwide, carriers will be pushing to get the costs of these systems down, as it's going to be a high-volume market. And the key to cost is getting voice and data in the same system."

This is the premise of ADI's TigerSharc line, which McCann said has special provisions for both symbol-rate (data) and chip-rate (voice) processing, "with the ability to assign processing power on the fly as the requirements change. TI's device is heavy on chip-rate processing, with limited support for symbol rate," he said.

In terms of peripheral support, each version of the 64X has its own mix. The C16, for example, has Utopia 2 or McBSP 2, PCI and general-purpose interfaces. It also has 64- and 16-bit external memory interfaces, along with three timers and power-down logic. The C6415 has the same ATM Utop ia 2 and PCI connection option, but targets imaging and video applications.

Initial samples of all three devices are scheduled to begin this June, in 400-, 500- and 600-MHz versions. All will be packaged in a 532-lead, 23 x 23-mm ball-grid array. Pricing for the family, beginning with the 400-MHZ C6414, starts at $95 each in quantities of 10,000.