2D Vector Graphics Accelerator / GPU (Graphics Processing Unit)
TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite
Eastleigh UK - Paris France, January 24, 2005 – TransEDA, the leader in coverage and ready-to-use verification solutions for electronic designs, today announces SystemVerilog support in new versions of its VN-Cover and VN-Check tools.
By delivering these new versions, TransEDA has met the commitment it made at DAC'04 to provide support for the emerging SystemVerilog standard.
SystemVerilog support in VN-Cover, the industry’s most accurate code coverage solution, means that designers can take advantage of powerful new SystemVerilog constructs such as enumerated types, records, user-defined types, etc., and still accurately measure code coverage on their design in the same way they do with VHDL and Verilog. Coverage measurement for SystemVerilog / VHDL, mixed-language designs is also fully supported.
SystemVerilog support in VN-Check, the configurable rule checker, enables designers to check name and style rules for this language very early in the design flow. This extended capability is extremely useful to ease migration of design teams to SystemVerilog and to ensure consistent use of this new language on a company-wide basis.
The new version of VN-Check also implements numerous assertion-oriented rules, aimed at helping designers to include assertions in order to correctly cover their designs.
Another major enhancement in the new version of VN-Check is the implementation of advanced rules, which are verified using an embedded formal engine.
This new set of high-end rules allows users to perform extended design consistency checks on RTL, and complements traditional rule checking by formally verifying the functionality of selected features of a design.
Examples of the rules provided in this advanced rule set are:
- FSM safety and liveness (state and transition reachability, dead lock)
- Synthesis Pragma violations (full case, parallel case)
- Array index out-of-bounds
- Bus contention detection
- Deterministic initialization (minimal number of cycles until circuit is stable at reset)…
With this enhanced version of VN-Check, designers have access to the best value configurable rule checking solution. The extended sets of rules, encompassing syntax, semantics and automatic formal rules checking, allow very early detection of design issues.
Availability
SystemVerilog VN-Cover, VN-Check versions and the VN-Check Advanced Rules option are available now in beta. For more information, contact your local TransEDA sales representative.
TransEDA will demonstrate these new key capabilities at DATE (Design Automation and Test in Europe) that will take place in Munich from the 8th - 11th of March 2005 – Booth # D7000.
|
Related News
- New Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces
- Green Mountain adds simulation tool to verification suite
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Faraday Adds Video Interface IP to Support All Advanced Planar Nodes on UMC Platform
- SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio
Breaking News
- VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system
- Avant Technology Partners with COSEDA Technologies to Enhance System-Level Software Solutions
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
- Qualcomm initiates global anti-trust complaint about Arm
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Sarcina Technology launches AI platform to enable cost-effective customizable AI packaging solutions
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |