English
BOPS Seminar Offers VoIP SOC in a Box Instruction
BOPS Seminar Offers VoIP SOC in a Box Instruction
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Feb. 12, 2001--BOPS, Inc., a leading provider of programmable broadband DSP cores, is offering free seminars on its recently announced SOC (System On Chip) in a Box(TM) for VoIP (Voice over Internet Protocol) application. In concert with its partners Tality and HelloSoft, BOPS will describe the family of licensable SOC in a Box(TM) pre-packaged applications created to drastically reduce time-to-market and technical risk involved in designing chips for VoIP applications.
The seminar will focus on the:
- VoiceRay(TM) CGW set of cores for carrier-class gateway applications with up to 192 channels of G.729a or 512 channels of G.711, both with 32ms of G.165/168 echo cancellation on a single chip;
- VoiceRay SMB for small-to-medium business applications with up to 96 channels of G.729a; and
- VoiceRay SOHO for small-office, home office applications with up to 24 channels of G.729a.
The next seminar is scheduled for February 22, 2001 at the Westin Hotel in Santa Clara. For more information and to register, go to www.bops.com/sb1.
About BOPS
Based in Mountain View, Calif., BOPS, Inc. develops and licenses a fully scalable, synthesizable DSP architecture that is programmable and reusable for evolving communications, mobile multimedia and wireless applications. BOPS' DSP architecture, cores, compilers, system tools and complete SOC designs offer total life-cycle solutions and rapid time-to-market. While providing the highest performance in the industry, BOPS cores are DSP co-processors to ARM, MIPS and other hosts and are supported by an extensive alliance of hardware, software, tools and design partners. For more information, please visit http://www.bops.com.
Note to Editors: BOPS is a registered trademark, and SOC in a Box and VoiceRay are trademarks of BOPS, Inc.
Contact:
BOPS, Mountain View Anita Giani, 650/254-2815 anita.giani@bops.com
Related News
- BOPS Announces Industry's First SOC in a Box
- 28FDSOI "SoC White Box" SERDES & Controller IPs' are available for immediate licensing
- The Industry's First SoC FPGA Development Kit Based on the RISC-V Instruction Set Architecture is Now Available
- VeriSilicon's Artificial Intelligence Processor IP Used in Next-Generation Large Screen Smart Home System-on-Chip (SoC)
- Dolphin Integration offers a live webinar on how to get an SoC power consumption under 0.5 uA in sleep mode
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |