English
Improv board holds five Jazz processors
 |
Improv board holds five Jazz processors
By Patrick Mannion , EE Times
February 5, 2001 (5:31 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010202S0031
MANHASSET, N.Y. — Improv Systems Inc. (San Jose, Calif.), a licensor of intellectual property for configurable DSP platforms, has announced a five-processor silicon implementation of its configurable Jazz Processor architecture. Called the Quintet, the silicon is available for evaluation in the Jazz Quintet Rehearsal Board, which delivers up to 1,400 million operations per second (Mops) at 100 MHz, Improv said. The processor is comprised of a control section, data memory modules and a set of computation units. Each 32-bit, fixed-point Jazz processor is based on a VLIW architecture and has a built-in multiprocessor capability. The processors are built in a 0.2-micron, five-layer metal CMOS process by Philips Semiconductors, and each consumes 2.75 W. The performance of each processor ranges from 700 to 1,400 Mops. The Jazz Quintet Rehearsal Board includes a PCI interface to download application software on a standard Windows NT PC. It also f eatures a predefined external bus interface to allow users to connect external devices or other resources directly to the Jazz Quintet device, enabling full or partial emulation of a target system. The board has been integrated into Improv's Jazz development environment, which allows users to specify that code execute on Jazz Quintet silicon rather than the internal simulator in the Jazz IDE. The board is supported with a high-level language compiler that generates code for all five processors from a single source code file. The five-processor implementation is targeted at advanced applications such as wired and wireless communications, and audio and video processing. The Jazz Quintet Rehearsal Board can also be used in conjunction with the company's recently announced Acappela solution for voice-over-packet applications to execute speech codecs, echo cancellation and related voice-over-IP algorithms, the company said.
Related News
- Silvaco Announces Appointment of Five Industry Veterans to Its Board of Directors
- AndesBoardFarm Enables SoC Designers to Explore RISC-V Processors in Online FPGA Board Collection
- Hex Five Announces MultiZone Security for Arm Cortex-M Series Processors
- Hex Five Announces General Availability of MultiZone Security for Linux - The First Commercial Enclave for RISC-V processors
- Express Logic's ThreadX RTOS Supports ARM and TI DSP Processors on Critical Link's MityDSP-L138F Board
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |