A broader look at ESL design

Taken in a narrow context, ESL represents a tiny fraction of the EDA market, so any slight perturbation of the definition of ESL tends to have a disproportionate impact on market share numbers. From the point of view of broad line EDA suppliers, and more importantly the system design houses, who are the ultimate potential users of this technology, these market share and growth numbers provide more heat than light.

This in no way is intended to diminish the importance of ESL, merely to point out that this is the wrong way to look at the design space. The niche tools that have claimed to be magic bullets in this space have been largely disappointing. The real progress in this area has come from advances in verification technology and tool interoperability based on open standards.

The next big advance that I see is the maturation of the intellectual property (IP) market based on industry programs exemplified by the Spirit Consortium. By advancing packaging, distribution, and verification standards of IP, this group is strongly supporting one of the necessary building blocks for ESL. These advances are the building blocks that are beginning to make ESL a reality.

Many of these enabling technologies will be on view at DVCon 2005 this week (Feb. 14-16, 2005) including several tutorials on the use of assertions, transaction level modeling in SystemC, and coverage based verification. There will also be a panel session on ESL, but I hope the panelists view the topic in the broad sense of what is needed to enhance system level design, rather than the narrow sense that ESL is often cast in, which only includes architectural exploration and behavioral synthesis.

The importance of advanced verification techniques cannot be overstated in any real system design process. Along with the need for interoperability between tools and languages, these techniques seem to be getting the recognition they deserve, especially during the last year.

Key milestones in the process can be seen in the beginning of formal standardization processes for SystemC, SystemVerilog, and PSL — all of which now have active IEEE working groups. I also expect to see, in the near future, similar advances in the standardization of interoperability enablers, such as the TLM libraries for SystemC. This will promote the ability for modelers to move easily between levels of abstraction, which is key for effective ESL.

The need for similar advances in making IP available for system design has long been discussed, but not much substantial progress had been made until the advent of the Spirit program. This group of EDA leaders and IP users and providers recognize the need for automating the process of IP selection to enable the efficient utilization of IP from multiple suppliers in the process of building complex SoCs.

They have quickly put together a schema for describing configurable IP in a machine-readable format to promote the automation of IP selection and use. They are now enhancing this work to support verification and ESL methodologies based on this schema.

ESL, in the sense of architectural exploration and tradeoffs, only becomes a practical reality when the foundational building blocks are in place. This implies that a complete design chain, based on open standards, must exist. This design chain must include:

• Models at several levels of abstraction, plus the methodologies for doing meaningful mixed-level simulation with them.
• Open access to IP from multiple vendors in a standard, efficient format that provides sufficient information about the IP for meaningful selection.
• Design language standardization and interoperability to support efficient verification.
• Tool platforms to support advanced verification, using the above components.

Victor Berman is general chair of the DVCon Conference, as well as group director of language standards for Cadence Design Systems, Inc.