Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
Intel targets multithreaded software for multicore processors
R. Colin Johnson, EETimes
3/3/2005 11:00 PM EST
PORTLAND, Ore. — By solving the parallel processing problem with application-specific languages, Intel Corp. Senior Fellow Justin Rattner predicted that future multicore processors will divide and conquer rather than depend faster single-processor speeds.
Speaking at the Intel Developer Forum Thursday (March 3), Rattner focused on how Intel is addressing parallel processing and bandwidth challenges. Intel reported successful fabrication of its first samples of a dual-core Pentium, called the Extreme Edition, and plans to begin delivering it during the first half of 2005.
Intel also said it has ten additional multicore processors in the pipeline for 2006 and beyond that will address different segments of the server, network, desktop and mobile markets. Rattner's job is to make sure the parallel processing capability of the multicore engines is fully utilized by software.
"The general-purpose approach we had been pursuing hadn't made much progress despite many years of effort. But now I think we have a winning approach. That is, we want to solve parallel processing with application-specific languages, as opposed to trying to create a general-purpose, parallel programming language."
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- AceThought introduces multi-threaded software video decoder suite for ARM Cortex-A9 MPCore and Cortex-A15 MPCore multi-core processors
- Multicore Association Provides Architecture Description Standard to Enhance Software Tool Support for Multicore and Manycore Processors
- CriticalBlue Provides Multicore Software Development Analysis Environment for OCTEON and OCTEON II Processors
- Open Virtual Platforms (OVP) Initiative for Multi-Core Software Development Releases High Performance Models of ARM Processors
- Wind River Debuts Multicore On-Chip Debugging Support for Intel IOP342 Processors
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks