System-in-package (SIP) may not be that simple

M2000 CEO Frederic Reblewski

In fact, you will often hear precautionary tales about SIP development from its backers. These include the lack of design tools specific to the task of handling complex interconnect issues, power estimation and simulation, among others. There are also compromises made with respect to power versus performance, and a major drawback when it comes to the board real estate needed by the SIP.

This is not to argue for the elimination of SIP as a design style: quite the contrary. There are many times when speed is of the essence, particularly in the fast-paced world of consumer electronics, when "first to market" can often obliterate "best to market."

In this sense, the SIP can be a useful stopgap while parallel development of a more practical SoC is happening. There is also a place for SiP in low to mid-volume applications that do not justify the time and expense necessary for the development of a complex SoC.

But in the "long run" — that span of time where semiconductor fortunes are made — the SoC clearly triumphs. There are also some remarkable changes coming in SoC design. In a recent DesignCon 2005 speech, Mentor Graphics Corp. CEO Wally Rhines forecast a time in the not-so-distant future when new architectures will enable customizable, reconfigurable chips.

"New custom-programmable architectures are emerging at a rate of one every two to three weeks," Rhines noted. Examples include fabrics such as structured ASICs, platform ASICs, array-based platforms, cell-based platforms and embedded FPGAs. Rhines foresees a shift to design platforms built by a few thousand engineers, used by many times more to create systems.

This customization is becoming easier to accomplish thanks to a new class of embedded FPGAs (eFPGAs) designed for nanometer processes, low power and flexibility. And there are clear advantages in having programmable parts embedded in silicon rather than added to a crowded package. These are chiefly lower power and cost, combined with enhanced performance and connectivity.

Our experience indicates that SoCs with eFPGAs achieve 40 percent better performance than a comparable SIP, mainly because of savings in interconnect delay. Power is similarly reduced through the elimination of drivers required in the SIP I/O pads. And of course, cost and area are dramatically reduced through silicon integration.

All of these gains are due primarily to the elimination of I/O pad rings connecting the standalone FPGA to the SIP. In fact, the eFPGA can have hundreds of interconnects, while the I/O pad ring severely limits the number of possible connections.

Add to this the fact that electronic-system-level design is growing in popularity and sophistication, and one can assume that the creation of reconfigurable SoCs will become less arduous and more cost-effective in the near future.

Frederic Reblewski is chief executive officer for M2000 (Sunnyvale, Calif.)