Structured ASICs walk a fine line

Fremont, Calif. — As structured-ASIC product lines begin to mature and sort themselves out, a predictable problem is emerging — product line management. Because the structured devices, by definition, have some functional resources built in beforehand, they are not universal. No single device can meet all the needs in the market.

Further, it appears that there is a fairly direct trade-off between performance and generality. A fully general-purpose structured ASIC would need to be entirely flexible in I/O configurability, in creating voltage and clock domains, and in the ability to shift resources between RAM and logic in a given area of the die. Such a design is possible, but in each case, that kind of flexibility would come at a cost in density and performance. A purely configurable device would probably be impractical.

At the other extreme, it would be possible to provide a platform ASIC for a particular application by simply optimizing a system-on-chip for that application, and then choosing functional blocks that might be subject to some degree of variability and implementing just those small and — one hopes — non-speed-critical blocks in a mask-configured logic fabric. All the major functions would be implemented as cell-based, highly optimized logic, perhaps with custom critical paths, and all the memory structures would be tuned to perfection. Again, such a device is possible, but it would serve such a narrow market that it would probably be infeasible. And in any case, it would probably be called an application-specific standard product rather than a structured ASIC.

Between these two extremes, structured-ASIC vendors are trying to find the right mix of hardwired functionality and configurability. It's not an easy task, and just about every vendor comes up with a different answer.

The cases of LSI Logic Corp. and ChipX might illustrate the point — one large and powerful, the other small but a proven survivor.

To start with the small, ChipX (Santa Clara, Calif.), the company formerly known as Chip Express, has been tuning its product line since the early days of the structured-ASIC market. This is a particularly critical issue for a small company because, in addition to the risk of missing a market niche, every version of the master slice runs up the company's investment in the product line and increases the product management expenses. So, not only must a company like ChipX make sure its wares are not too general-purpose to offer attractive performance, it also must make sure it isn't launching too many specific products.

For some time, the company has been responding to this challenge by examining the weak points in the competitive matrix. One that ChipX identified last year was the relative lack of RAM in many product lines. So, the company launched a structured-ASIC line with a proportionately quite large block SRAM content.

Now ChipX is taking this thinking into more application-specific areas, according to vice president of marketing Elie Massabki. "We want the capability to go after the really high-volume business, not just FPGA conversions," Massabki said. "That means becoming more like a cell-based ASIC in some respects."

ChipX started in a good position for this move, with what is probably the finest-grained logic cell in the market. The first new step in that direction has been for ChipX to adopt the Magma Design Automation Inc. design flow from end to end, even to the point of making architectural changes to reflect Magma's hierarchical approach to design.

Following this approach in the future, look for base arrays targeted at particular application segments with hardwired functional blocks, specialized I/O pads and even specific package choices, all aimed at specific markets. The company is betting that it can overcome its small size by offering significant advantages for specific application areas.

One of those advantages will have to be price, Massabki said. "The cheapest structured ASIC in the market today is still around $50," he said. "There is room in the market for less-expensive solutions."

Landing Zone concept
LSI Logic, meanwhile, is continuing to elaborate on its master plan for RapidChip — two families of master slices with good chunks of block SRAM, diffused I/O functions and "Landing Zones" — locations in the logic fabric into which preoptimized macros can be dropped for particularly challenging functions.

In the past, the Landing Zone concept has been used primarily to accommodate an ARM CPU. But in the Xtreme2 family, the idea has also been employed to support hard macros for such challenging I/O functions as PCI Express, RapidIO and SPI 4.2. Preoptimized hard macros are dropped into place just inside the configurable I/O blocks to ensure timing closure.

Xtreme2 adds 12 new slices — with three more on the way — to a product line that already includes some 33 slices in the Foundation, Integrator 1, Integrator OS and Xtreme families.

"It becomes very important to have the members of a family spaced fairly closely in capabilities and cost," said Thomas Colino, director of architecture at LSI Logic (Milpitas, Calif.). "When a customer design starts adding functionality, it is important for them to be able to move to the next larger device without a large increment in cost or a change in underlying architecture."

On the other hand, it is important to LSI that every member of each family should be just right for something in particular, so there are no expensive orphans in the product line.

"The majority of the science went into fitting the definitions of the individual family members to specific, marketable applications," Colino said.

"To do this, we looked at application needs in considerable detail — comparing which functions, what memory blocks and what I/O instances were actually used in a particular application, and matching that against our inventory of IP [intellectual-property] blocks in the product line," he said.

This led to changes in the Xtreme2 family, Colino said. One simply increased the amount and the flexibility of memory, so that larger blocks, larger numbers of instances and higher throughputs could be achieved while still keeping the back-end design problem manageable for LSI. Another change added considerably to the variety of fast I/O protocols that could be supported — many with Landing Zone controller blocks — and increasing the variety of combinations in which they could be used.

The result is something like an extensive data book. You can name a chip site in a system design where an ASIC could be used, and Colino can come up with the RapidChip family members that support the right combination of I/O functions, memory and logic for that spot on the board. It's a game that has to balance LSI's development and product life costs against market address, but it's a game that LSI has studied carefully.