English
Xelic Announces SONET/SDH Tributary Payload Processor Core Availability for Integration into ASIC or FPGA Networking Applications
Rochester, NY -- March 22, 2005 -- Xelic, Inc., a leading provider of Networking Intellectual Property and Engineering Design Services today announced the immediate availability of their SONET/SDH Tributary Payload Processor Core for product integration.
The Xelic SONET/SDH Tributary Payload Processor Core (XCSTPP12) performs tributary pointer processing, aligns outgoing tributaries and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate. The XCSTPP12 implements the industry standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2 or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
“The XCSTPP12 adds to Xelic’s growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level.” said Doug Bush, Director of IP Development at Xelic.
Xelic cores are available under flexible licensing terms and come complete with full documentation and a comprehensive suite of self-checking tests. Core customization and integration services are also available.
Xelic is a privately held Networking Intellectual Property provider and Engineering Services Company. Xelic offers standards based IP for SONET/SDH, Digital Wrapper, Generic Framing Procedure, ATM, and Forward Error Correction applications. Xelic’s Engineering Services include Product Definition, ASIC/FPGA Development, System Design, Board Design, Firmware Design, and full turnkey solutions. Xelic was founded in January of 2001 and is based out of Rochester, NY. For more information about Xelic, please visit www.xelic.com.
Xelic and XCSTPP12 are trademarks of Xelic, Inc. All other trade names, trademarks, and registered trademarks are the property of their respective owners.
The Xelic SONET/SDH Tributary Payload Processor Core (XCSTPP12) performs tributary pointer processing, aligns outgoing tributaries and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate. The XCSTPP12 implements the industry standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2 or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
“The XCSTPP12 adds to Xelic’s growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level.” said Doug Bush, Director of IP Development at Xelic.
Xelic cores are available under flexible licensing terms and come complete with full documentation and a comprehensive suite of self-checking tests. Core customization and integration services are also available.
Xelic is a privately held Networking Intellectual Property provider and Engineering Services Company. Xelic offers standards based IP for SONET/SDH, Digital Wrapper, Generic Framing Procedure, ATM, and Forward Error Correction applications. Xelic’s Engineering Services include Product Definition, ASIC/FPGA Development, System Design, Board Design, Firmware Design, and full turnkey solutions. Xelic was founded in January of 2001 and is based out of Rochester, NY. For more information about Xelic, please visit www.xelic.com.
Xelic and XCSTPP12 are trademarks of Xelic, Inc. All other trade names, trademarks, and registered trademarks are the property of their respective owners.
|
||||||
Related News
- Xelic Announces Family of SONET/SDH Transport Processor Cores for Integration into FPGA or ASIC Networking Applications
- Xelic Announces Frame Mapped Generic Framing Procedure Core Availability for Integration into ASIC or FPGA Networking Applications
- Avalon Microelectronics Announces Availability of 40G SONET/SDH Framer/Mapper/Pointer Processor
- Xelic Announces Successful Integration of Industry's First 40Gb/s SONET/SDH Framer Core into Customer Equipment
- Xilinx Kintex-7 FPGA Embedded Kit Accelerates Productivity and Programmable System Integration for FPGA-Based Soft Processor Systems
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
|
E-mail This Article | 
|
|
Printer-Friendly Page |