Configurable processor scores best in office test, Tensilica says
EE Times: Configurable processor scores best in office test, Tensilica says | |
Peter Clarke (03/24/2005 2:16 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=159905503 | |
LONDON The Xtensa LX configurable processor core available for license from Tensilica Inc. (Santa Clara, Calif.) has achieved the highest score for any processor on the Office Automation benchmark suite of the Embedded Microprocessor Benchmark Consortium, according to Tensilica. Although a so-called "out-of-the-box" Xtensa LX scored lower at 0.98880 for the OAmark than an out-of-the-box PowerPC 440GX processor, which recorded 1.07999, when the Xtensa LX was optimized its performance score was more than quadrupled to 4.19523, 3.88 times the performance of the PowerPC 440GX, Tensilica said. In addition an "out-of-the-box" 64-bit MIPS 20Kc processor scored 0.89033 and an out-of-the-box ARM 1026EJ-S processor scored 0.75975, Tensilica said, adding that the EEMBC benchmark scores are independently certified by the EEMBC Certification Laboratories (ECL). The EEMBC scores for licensable synthesizable processors are expressed on a "per-megahertz" basis, and the configuration of Xtensa LX used in this Office Automation benchmark certification achieved a 454-MHz operating frequency in a 90-nanometer ASIC technology, Tensilica said. The 4.19523 OAmarks-per-megahertz at 454-MHz yield an "at-speed" score of 1904 OAmarks, which surpasses the previous highest absolute score posted by a 1.4-GHz Freescale PowerPC, the MPC7447A, Tensilica observed. Tensilica's Xtensa LX processor also demonstrated smaller code size than the same competitor processors. "For our 1.4 square millimeter Xtensa LX processor to have the equivalent speed of a much larger PowerPC core when running the out-of-the-box C code, while having a 4X code size advantage, is a testament to the inherent advantages of the Xtensa base processor architecture," stated Steve Roddy, vice president of marketing for Tensilica, in a statement. Tensilica used the EEMBC-provided, ECL-certified C Code with its XPRES Compiler to generate the optimized version of the Xtensa LX processor for this benchmark. ANSI-standard C code tuning was performed to expose the natural parallelism inherent in the EEMBC benchmark code. No C intrinsics, no assembly coding, or other Xtensa-specific changes were made to the reference EEMBC C code. The resulting C code could be run on any processor, not just an Xtensa LX processor, the company said in the statement.
| |
- - | |
Related News
- TU Dresden Realized 28nm Low Power Test Chip with Tensilica Processor and RacyICs Power Management in GLOBALFOUNDRIES Process
- TSMC test runs Apple processor, says report
- Tensilica Configurable Processors Used in Stanford Smart Memories Project
- Tensilica Enhances Xtensa Configurable Processor Families with New Options, Bridges and Software Tools
- Tensilica Offers Integrated Real-Time Trace Support to Xtensa Configurable and Diamond Standard Processor Cores
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |