D&R Headline News (December 2006)

Headlines for Friday Dec. 29, 2006

• Wi-LAN Completes Closing of $30 Million Bought Deal Financing
• TSMC Welcomes Government Approval for 0.18 Micron Generation Technology Transfer to China

Headlines for Thursday Dec. 28, 2006

• Multicore faces a long road
• Analyst Gary Smith: top 10 EDA topics for 2007

Headlines for Tuesday Dec. 26, 2006

Top Story

ASIC Architect Announces Availability of Configurable AMBA 3 AXI Bridge for DDR Controller Cores

ASIC Architect Expands its DDR Offerings with AMBA© 3 AXITM Bridge for DDR Controller Cores

Headlines for Thursday Dec. 21, 2006

Top Story

Leading U.S-Based Semiconductor Company Takes $11M Multiyear License for ARC International's Patented Configurable Solutions

ARC Reaffirms Financial Year 2006 Outlook And Sets Date for Announcement of Preliminary Results

• Silicon Image and Genesis Microchip Sign Settlement and License Agreement; Silicon Image Expects $13-$15 Million Increase in Fourth Quarter 2006 Operating Income
• Dolphin Integration Announces their new generation of CODEC providing a Signal to Noise Ratio of 100 dB
• Chipworks 65-nm Virtex-5 Study Validates Customer Benefits of Xilinx Dual-Foundry Strategy
• BitSim releases BADGER, a HW Reference platform to evaluate, develop and demonstrate solutions for Displays in Embedded Systems
• Array Electronics's DDR SDRAM Controller XS receives Xilinx AllianceCORE product certification
• Green Hills Software Announces Support for ARM Cortex Processor Family

Headlines for Wednesday Dec. 20, 2006

• Fabless Semiconductor companies: is intellectual property reuse creating a new model?
• Cypress Introduces Five New PSoC Development and Evaluation Kits
• eASIC Strengthens Technical Ranks By Attracting Industry Luminary

Headlines for Tuesday Dec. 19, 2006

Top Story

ARM Announces First Production-Ready DDR1 And DDR2 Memory Interface IP On TSMC 90-Nanometer Process

The ARM Velocity DDR1/2 memory interface is the first 90-nm production-ready IP to pass TSMC's IP quality assurance test

• ARM Cortex Processors Chosen by Texas Instruments For Use in Critical Automotive Applications
• SiCortex Inc. Licenses MIPS64 Architecture for Low-power, High-performance Teraflop Computing
• Lattice and ANAGRAM Will Provide Crystal Clear Audio Solutions to the Consumer Market
• PLDA and AGFA Graphics Sign Silica-Brokered Deal
• Wipro Becomes Tensilica Processor Core Design Center Partner
• LogicVision Announces Tundra Semiconductor Successfully Delivers Silicon With LogicVision 1149.6 Boundary Scan
• Faraday Adds Fast Ethernet PHY and Controller Cores to its Licensable IP Portfolio
• Patriot Scientific Highlights Successful Calendar Year as Schneider Electric Joins Stellar Roster of Moore Microprocessor Patent Portfolio Licensees

Headlines for Monday Dec. 18, 2006

Top Story

Denali Launches MLC NAND Flash Solutions for SoC Designs

Databahn NAND Flash Controller IP and Spectra NAND Flash Management Software Speeds Deployment of MLC NAND Flash Memory in Electronic Products

• eInfochips Supports the Mentor Graphics' Questa(TM) Vanguard Program for AMBA AHB SystemVerilog Verification Component
• CoWare and VeriSilicon Announce Partnership to Strengthen ESL Design Solution for ZSP Processors
• Imagination Technologies' Multi-Standard Video Core Passes Allegro H.264 Test Suite
• Sarance Technologies Delivers Interlaken Protocol IP Core for Xilinx Virtex-5 FPGAs
• ASIC Architect Announces the Availability of Configurable AMBA3 AXI Bridge for PCI Express Controller Cores
• SPI-S From the OIF Is Ready for Business

Headlines for Friday Dec. 15, 2006

• Q&A: Denali's Srivastava bridges EDA, IP domains
• Nordic Semiconductor launches VoIP wireless headset reference design that promotes fast, low risk development of USB wireless PC headsets offering 70-hour battery talk-time from two coin cell batteries

Headlines for Thursday Dec. 14, 2006

Top Story

PLDA Announces PCI-SIG Compliant Programmable Switch IP for PCI Express

The Programmable Switch IP, which includes an upstream and downstream instance of PLDA's XpressRich shared-silicon IP Controller connected with a glue logic, is a highly configurable solution suitable for connecting x1, x4, and x8 lane components

• Jetstream Media Technologies Announces a Full Line of Security IP Cores for ASIC and FPGA
• Phylinks Taps Nabil Takla as Chairman
• Toshiba, Sony and NEC Electronics Unveil Mass Production Platform Technology for 45nm Generation High Performance System LSI
• Austrian Research Centers GmbH and Gaisler Research AB signs license agreement for LEON3 and the GRLIB IP library
• Bluespec Begins Volume Shipment of SystemC Synthesis

Headlines for Wednesday Dec. 13, 2006

Top Story

L&T Infotech Acquires GDA Technologies

Larsen & Toubro Infotech today announced that they have signed a definitive agreement to acquire GDA Technologies, Inc., and all of its design centers in US and India.

• Dongbu Electronics Adds ARM Metro Low-Power Library To Design Support Portfolio
• MoSys Enables Advanced Mobile Handhelds through License Agreement with NexusChips
• LogicVision Enhances ETAccess for Fast Silicon Bring-Up and Diagnostics
• Altera Ships Production-Qualified Stratix II GX FPGAs
• Handshake Solutions partners with Mentor Graphics to extend commercial testing for clockless ICs
• MataiTech launches NAUET 1.7, including the world's first SPIRIT IP-XACT linter, and a royalty free, light weight RTOS, IP-XACT 1.4 Ready

Headlines for Tuesday Dec. 12, 2006

Top Story

Innovative Introduces Breakthrough Pricing Model for Mixed Signal IP

Flexible Model Allows Designers to Evaluate IP Cores Prior to Making a Full Licensing Commitment

• Arasan Announces Support for SDIO Version 2.0 in its SDIO Device IP
• Triad Semiconductor Forms Triad Alliance Program for ASIC Partners
• India's Cosmic Circuits licenses IP

Headlines for Monday Dec. 11, 2006

Top Story

ARM High-Speed PHY and High-Performance Standard Cells For 65-Nanometer Platform Adopted By Fujitsu

The ARM Velocity PHY family of products meets the stringent requirements for high-speed serial standards such as PCI Express, Serial ATA and XAUI. The PHY products offer exceptional jitter performance, low-power consumption and extensive testability within a small physical size, thereby enabling error-free data transfers over a wide range of operating conditions and environments.

• Patriot Scientific's Planned Momentum Increases as Lexmark Purchases MMP(TM) Patent Portfolio License
• CoWare Integrates Microsoft Windows Embedded CE on Virtual Platforms for Software Development
• IPextreme to Bring Expanded Portfolio of Advanced Infineon IP to Rapidly Growing Automotive Electronics Market
• TurboConcept's TC1000WiMAX turbo decoder Core incorporated in Sequans' WiMAX chips
• Virage Logic and Tensilica Introduce Core-Optimized IP Kits for Tensilica's Diamond Standard Processors
• Broadcom Delivers the Industry's First Single-Chip, 65 Nanometer High Definition 1080p Digital TV Solution

Headlines for Friday Dec. 08, 2006

• Brazil design team joins IP silicon club
• WI-LAN Announces $30 Million Bought Deal Financing
• How Real is the Intellectual Property Revolution?

Headlines for Thursday Dec. 07, 2006

• Gaisler Research AB is awarded a contract for developing the LEON4 processor
• Agere Systems Announces Low-Cost Cell Phone Platform for the Market's Largest Segment
• Rambus CEO: Consumer arena now drives IC demand
• MIPS Technologies Files Lawsuit Against Trident Microsystems

Headlines for Wednesday Dec. 06, 2006

• Nokia Licenses Wi-LAN's Patent Portfolio
• Xilinx Delivers Spartan-3A Platform - World's Lowest Cost I/O-Optimized FPGAs
• New Silicon Image HDMI 1.2 Transmitter for Set-Top Boxes and DVD Players Reinforces World's Broadest HDMI Semiconductor Line

Headlines for Tuesday Dec. 05, 2006

Top Story

Mentor Graphics Introduces its High-Speed USB-Certified PHY for Embedded Host Applications in the SMIC 0.13 micron Process

This “proven-in-silicon” USB 2.0 PHY implements a UTMI+ Level3 USB Transceiver Macrocell Interface, and offers support for device, host, embedded host and OTG USB controllers

• Sunplus Ships A/V Products With Kilopass One-Time Programmable Non-Volatile Memory
• Chipidea Achieves Industry's First USB High Speed PHY Certification in TSMC 65nm Technology
• The SPIRIT Consortium adds FPGA Solution Providers to its Roster, along with a GPS Solution Company and a Consultancy
• OCP-IP Announces Six New Members

Headlines for Monday Dec. 04, 2006

Top Story

LSI Logic and Agere Systems to Combine in All-Stock Transaction Valued at Approximately $4.0 Billion

The companies had combined revenue of $3.5 billion for the 12 months ended September 30, 2006. The companies operate in more than 20 countries, with a combined workforce of approximately 9,100 employees, including nearly 4,300 engineers. The companies together own a substantial patent portfolio consisting of more than 10,000 issued and pending U.S. patents.

• True Circuits Announces New Line of 65nm Timing IP; Customers' Product Shipments Planned for 2007
• Novelics Introduces Silicon-Proven coolSRAM-1T for SoC Designers with Large Embedded Memory Needs
• Mercury Computer Systems Is Selected by Applied Micro Circuits Corporation (AMCC) to Provide Serial RapidIO Verification IP and IP Cores
• austriamicrosystems announces license agreement with Infineon for FlexRay transceiver IC
• Rapport Adopts LogicVision Embedded Test Solutions for Next Generation Low-Power Device
• Z-RAM Gen2 Ultra-Dense Memory Technology from ISi Significantly Improves Speed and Power
• Tensilica Introduces Four Video Processor Engines Including Main Profile H.264 Support
• Tensilica Introduces Xtensa LX2 and Xtensa 7 Configurable Processors
• Low Power Hard Core Diamond Standard Processor for TSMC 0.18-micron Technology Available Through Global Unichip
• Open SystemC Initiative Announces Proposal for Significant Extensions to Transaction-Level Modeling (TLM) Standard
• Cadence Enterprise System-Level Verification Enables Predictable Software, Hardware and System Quality
• Sagem Défense Sécurité Integrate Celoxica ESL and MVI IP into Product Design Flows

Headlines for Friday Dec. 01, 2006

Top Story

Arasan Announces Support for Part A2 of the SDIO Version 2.0 Specification

The Part A2 enhancement extends the basic DMA Part A1 capability to an advanced Scatter-gather method. The new method improves the performance allowing transfer to/from multiple memory locations in a single DMA transaction.

• MOSAID Adds Mosel Vitelic to Patent Infringement Case Against Micron, Powerchip and ProMOS
• MOSAID Acquires Pseudo-SRAM Patent Portfolio