D&R Headline News (March 2007)

Headlines for Friday Mar. 30, 2007

• Dolphin Integration releases its RAM for 90 nm nodes with dual optimization: for ultra-low power and for extremely high density

Headlines for Thursday Mar. 29, 2007

Top Story

Synopsys Accelerates Low-power Designs with Comprehensive Implementation and Verification Solution

Synopsys DesignWare® IP is architected for low power consumption in both active and standby modes. This is achieved by using power-efficient transmitters, phase-locked loop (PLL) blocks and clock gating techniques. Synopsys' USB 2.0 nanoPHY, designed for the latest mobility devices, consumes half the power of previous USB implementations. The PCI Express™, Serial ATA (SATA), and XAUI high-speed serializer/deserializer (SERDES) PHY IP support low-power modes and consume significantly less power than similar IP on the market.

• Mentor Graphics Provides Comprehensive Product Support for New ARM Cortex-M1 Processor for FPGAs
• Virage Logic Adds Liberty Composite Current Source Model Support to Memory and Logic IP
• Altera to Initiate a Dividend and Repurchase Additional Shares
• EETimes Blog: ST picks up Chinese processor
• The death of ASICs is greatly exaggerated

Headlines for Wednesday Mar. 28, 2007

Top Story

Impinj Announces Semiconductor Industry's First Multi-Time-Programmable Nonvolatile Memory IP Qualified in 90 nm Process Technology

The first-ever multiple-time-programmable (MTP) NVM IP qualified and released for production at the 90-nanometer process node, Impinj's AEON/MTP cores provide the cost, power and functionality benefits of embedded NVM in standard logic CMOS (also known as Logic NVM.)

• MOSAID Completes Sale of Memory Test Assets to Teradyne
• Infineon Further Strengthens its Position as a Leading Player in the Indian Semiconductor Market; Licenses 130nm CMOS Process Technology to Hindustan Semiconductor Manufacturing Corporation
• CEVA's Fully Programmable Mobile Multimedia Solution Passes Allegro H.264 Test Suite
• ARC Announces New Licensing Agreements with Leading Semiconductor Companies in Asia
• MIPS Technologies Licenses MIPS64 Architecture to STMicroelectronics
• Synopsys IC Compiler Enables Fully Automated 65-Nanometer Implementation Flow For ARM Cortex-A8 Processor
• China's Institute of Computing Technology and STMicroelectronics Announce Their Cooperation on the Loongson Processors
• Silicon and Software Systems (S3) to invest €9 Million in R&D with support from Enterprise Ireland
• NEC Electronics America and Avnet Electronics Team to Deliver ASIC Solutions

Headlines for Tuesday Mar. 27, 2007

Top Story

eASIC and CAST Announce the Availability of H.264 Multi-Channel Baseline Video Encoder Core for NextremeTM Structured ASICs

eASIC today announced the availability of the H264-MCE multi-channel baseline video encoder core from CAST, Inc. for implementation in Nextreme Structured ASIC devices. This Intellectual Property core, which was proven in a 90nm Nextreme fabric, demonstrated 150MHz performance and is now offered as a low-cost and fast turnaround solution for a wide range of video processing applications.

• Wi-LAN and Tri-Vision Announce Merger
• Innovative Silicon's Z-RAM Ultra-Dense Memory Now Backed by 21 Patents
• Synopsys Enables STMicroelectronics to Achieve First-Silicon Success for 65-nm Dual High-Definition MPEG-4 Decoder
• MorethanIP 10 Gigabit IP Solutions provide unprecedented time to market for next generation Server Adapter Cards from Tehuti Networks
• Altera's Stratix II FPGAs Now Qualified for Military Temperature Grade
• TSMC Announces 55nm Process Technology Readiness
• ByteTools' Low-Cost Catapult Probe Supports Tensilica's Processors
• PLDA and Texas Instruments Showcase PCI-SIG Compliant Solution at Embedded Systems Conference

Headlines for Monday Mar. 26, 2007

Top Story

Mentor Graphics Announces Subsystem Intellectual Property Launch with First Delivery of Integrated USB Solution

Mentor Graphics today announced a technology launch of subsystem intellectual property (IP), beginning with the industry's first USB subsystem solution from a single-source EDA provider. Mentor Graphics is the only EDA company that develops its own digital controller, hardware PHY (physical layer), and embedded software IP to deliver an integrated and verified IP solution for today's complex electronics designs.

• Xilinx Simplifies Embedded Development with New EDK 9.1i Suite
• China's Premier IC Design Firm Licenses MIPS32(R) 24KEc(TM) Pro Core to Develop Next-Generation Multimedia Solutions
• Virage Logic and Tower Semiconductor Agreement Provides Mainstream NVM Availability for RF and Mixed-Signal Applications
• SST Redefines Memory Subsystem in Embedded and Mobile Applications with All-in-OneMemory Solution
• TI Single-Chip Solution Drives GPS into Mainstream Mobile Phones
• Intel To Build 300mm Wafer Fabrication Facility In China
• Ocean Blue Releases DVB multi-mode software for entry-level NXP Semiconductors STB100 & STB200 hardware platforms

Headlines for Friday Mar. 23, 2007

• Thin Multimedia to Develop a Multi-Standard Mobile TV Solution With Siano

Headlines for Thursday Mar. 22, 2007

Top Story

Agere Systems expands licensing agreement with Silicon Hive for HiveFlex processors

Agere Systems signed a new license agreement for Silicon Hive's HiveFlex CSP 2000 Series application specific communications processors. Agere's Telecommunications & Enterprise Networking business unit is using the HiveFlex CSP 2000 processor in communications applications.

• iVivity Selects Mentor Graphics Ethernet Intellectual Property Family for iDiSX State Machine Architecture
• MoSys Launches New Memory Macros Specifically Configured for Mobile Handset Displays
• Open Core Protocol International Partnership Releases OCP SystemC Channel Version 2.2
• The Controversy Over GPL 3
• MathStar Collaborates with LG Electronics on Technology Solution for Delivery of HD Programming to Hotel HDTVs
• Xilinx Delivers PlanAhead 9.1 Design Suite - Extends Performance Advantage of 65nm Virtex-5 FPGAs

Headlines for Wednesday Mar. 21, 2007

• VSIA Announces New Members Join in IP Ecosystem Standardization Efforts

Headlines for Tuesday Mar. 20, 2007

Top Story

Jetstream Media Technologies Delivers Three New IP Cores - A Scalable Modular Exponentiation Accelerator and OC-192-Data-Rate XTS/Combo IP Cores

Jetstream Media Technologies announced today the availability of three IP cores: modular exponentiation accelerator, ultra fast XTS IP, and ultra-fast dual-mode JetCombo-2 IP.

• Octalica Licenses MIPS32 Core for Next-Generation MoCA-Driven Applications
• Silterra and Novelics Demonstrate Low Power coolSRAM-1T(TM)
• BiTMICRO Networks Selects QualCore Logic to Develop Analog IP Cores
• Key ASIC Has Selected Mixel to Develop and License Advanced Mixed Signal IPs for Silterra Foundry
• Core Logic Now Runs SPIRIT Voice on its Mobile Processors
• Federal Trade Commission Grants Partial Stay in Rambus Case

Headlines for Monday Mar. 19, 2007

Top Story

ARM Extends Cortex Family with First Processor Optimized for FPGA

The ARM Cortex-M1 processor extends the range of the ARM Cortex processor family and enables OEMs to standardize around a common architecture across the performance spectrum. Actel has worked with ARM as lead Partner and is the first licensee of the Cortex-M1 processor for use by their FPGA customers

• Xilinx Delivers Complete Development Kit for PCI Express
• Altera Ships Industry's First 65-nm Low-Cost FPGA
• Denali's Industry-Standard PureSpec Verification IP Utilized by IBM for Latest CoreConnect Bus Architecture Toolkits for SoC designs
• CEVA Unveils New Family of Multimedia Solutions for High Volume, Low Cost Mobile Consumer Electronics
• Impinj Delivers Logic Nonvolatile Memory in Tower Semiconductor's 0.13-Micron Process
• Avalon Microelectronics Announces Availability of 40G SONET/SDH Framer/Mapper/Pointer Processor
• Nokia files Patent Exhaustion Case against Qualcomm in Germany and the Netherlands
• Actel and ARM Develop High-Performance 32-bit Processor Optimized for FPGAs
• QuickLogic Delivers Ground-Breaking ArcticLink Solution Platform Tailored for the Mobile Market
• Commentary: EDA is dead, software lives

Headlines for Thursday Mar. 15, 2007

Top Story

CAST Partners with S2C for IP Distribution in China

S2C will provide CAST customers in China with a secure evaluation platform for IP reference designs using S2C's innovative FPGA-based ESL products. The CAST H.264 encoder core reference design is already available on the S2C TAI Logic Module(TM), a scalable rapid FPGA prototyping module. S2C plans to make more CAST IP available in the future.

• MPEG LA Issues VC-1 Patent Portfolio License
• MIPS Technologies Granted Stay to Remain Listed on Nasdaq
• Tokyo Electron Device Announces the Industry's Highest Performance Virtex-5 LX 330 Evaluation Platform
• Elliptic Adds New Officers to Board of Directors
• SMIC and Cascade Microtech Partner to Establish New Mixed-signal RFIC Design Service Lab in Shanghai
• Open-Silicon Inc. Secures $10 Million in Growth Financing
• Rockwell seeks 50 percent design cycle reduction
• IBM starts making Cell processor on 65-nm process

Headlines for Wednesday Mar. 14, 2007

Top Story

Faraday Launches FIE7020 Audio Platform Solution Targeting Portable Audio Applications

Faraday provides high performance 32-bit RISC CPU-based audio solutions, FIE7020 platform, which supports NAND flash/SD MMC card/HDD-based audio solutions with add-on video playback functions.

• MoSys Inks Agreement With SMIC to Provide High-Density 1T-FLASH Memory IP
• Xilinx Delivers Virtex-5 LX330T Device - World's Largest FPGA with Serial Transceivers

Headlines for Tuesday Mar. 13, 2007

Top Story

SNOWBUSH Announces Silicon-Proven SerDes IP in TSMC 65nm G+ Process for PCI Express, SATA & Other Serial Standards

SNOWBUSH's 1.0-5.0Gbps multi-standard SerDes macro provides a complete physical media attachment layer for PCI Express, SATA, SAS and Fibre Channel serial interconnects, and supports XAUI, Rapid I/O, Gigabit Ethernet and Infiniband.

• Kawasaki Microelectronics Extends Presence into Burgeoning PON Market with MIPS-Based Topaz Subsystem
• Xilinx Announces Virtex-5 System Monitor Capability - Industry's First FPGA Analog Debug and System Management Solution
• Stratix II GX FPGAs Meet Rigorous CEI-6G-LR/SR Specifications
• Avery Design Delivers PCI Express Gen2 Verification IP and Compliance Test Suite
• Wi-LAN Closes $40 Million Bought Deal Financing
• Cosmic Circuits announces tie-up with MA-Plus of Japan

Headlines for Monday Mar. 12, 2007

Top Story

Lattice Announces Industry's Fastest Low-Cost FPGA DDR2 Controller

Lattice Semiconductor today announced the immediate availability of the industry's first 533 Mbps Double Data Rate 2 (DDR2) Synchronous Dynamic Random Access Memory (SDRAM) controller Intellectual Property (IP) core supporting a Low-Cost Field Programmable Gate Array (FPGA) family. This DDR2 SDRAM IP core is optimized for Lattice's award winning LatticeECP2 and LatticeECP2M LatticeSC Extreme Performance FPGA family.

• Altera's Structured ASIC Design Flow Now ITAR-Compliant for Military Applications
• Mentor Graphics First to Provide Co-Verification Support for MIPS32 34K Multi-Threading Processor Cores
• OCP-IP Highlights Toshiba's Use Of OCP In Leading-Edge Super Companion Chip
• Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design
• Tallika Becomes Tensilica Configurable Processor Authorized Design Center
• TES Announces New Reference Platform for Telematics Applications
• EtherWaves Acquires Sonarics Labs' Digital Radio Technology
• Cavendish Kinetics Appoints Dennis Yost as CEO
• Programmable processors: Make them for all, or one?
• Lattice Announces Production Release of 90nm LatticeECP2 Family
• Introducing Certess -- Focusing on the Functional Qualification of ICs
• Chinese set-top box makers, MPEG LA face off over patent fees

Headlines for Friday Mar. 09, 2007

• Techno Mathematical rolls IP for one-chip, full-HD codec
• MataiTech Launches NAUET (newt) 1.8, including an Automatic IP Import Wizard that Converts IP Blocks to the Spirit IP-XACT Standard
• Patriot Scientific Momentum Continues as SanDisk Purchases Moore Microprocessor Patent(TM) Portfolio License
• Philips and TSMC Announce Joint Plan to Facilitate Orderly Exit by Philips from TSMC Shareholding
• Rambus Receives NASDAQ Notice of Non-Compliance

Headlines for Thursday Mar. 08, 2007

Top Story

Arasan Chip Systems Launches Industry's First Suite of MIPI IP Cores

The new products available include the Display Serial Interface (DSI) IP Core, the Camera Serial Interface (CSI-2) IP Core, and the D-PHY IP Core. The SLIMbus(TM) IP Core (Serial Low-power Inter-chip Media bus) supporting the preliminary draft specification is also available.

• CEVA Extends Connectivity Product Line With Bluetooth 2.0+EDR
• What next for symmetric multiprocessing on SoC?
• STMicroelectronics Unveils Two New Configurable System-on-Chip ICs in its SPEAr Family

Headlines for Wednesday Mar. 07, 2007

Top Story

Tundra Semiconductor Offers RapidIO Endpoint IP

The Endpoint IP enables high performance Serial RapidIO system interconnect between processors, bridges, remote memories, customer defined endpoint devices and Tundra RapidIO switches. The IP is compliant with RapidIO Interconnect Specification (Revision1.3) and supports up to 10 Gbps payload. Fully synthesizable, the IP is designed to be combined with technology specific SerDes on multiple process technologies.

• Faraday Monthly Sales Report -- February 2007
• Impinj Raises $19 Million in Private Funding Round; Prepares for Increased Demand for Item-level RFID Technology
• eASIC and GenCore Form Partnership for Distribution of Nextreme Structured ASIC Devices in Korea

Headlines for Tuesday Mar. 06, 2007

Top Story

SafeNet to be Acquired by Private Equity Firm Vector Capital for $634 Million

SafeNet today announced that it has entered into a definitive agreement to be acquired by an investor group led by Vector Capital in a transaction valued at approximately $634 million

• ARM tips plans for next-generation processor
• SNOWBUSH microelectronics announces availability of silicon verified, 80nm, Line-Lock PLL IP Block
• TSMC Achieves 65 Nanometer Embedded DRAM Milestone
• OCP-IP Introduces Open Network-on-Chip Benchmarks Initiative
• Arasan Chip Systems Extends USB IP Offerings to Actel's CompanionCore Program
• Faraday USB IP Successfully Cracks into Mass Storage, Multimedia, and Communication Markets
• ARC Configurable Technology at the Heart of Three Generations of IPWireless 3G Broadband Solutions
• ARC International Announces New Licensing Agreements with Leading European Semiconductor Companies and Design Teams
• Enuclia Picks Tensilica's HiFi 2 Audio Engine For Flat Panel TV Chips
• Toshiba Selects Xilinx Spartan-3 Generation FPGAs for Latest LCD TVs
• Xilinx Updates March Quarter Guidance

Headlines for Monday Mar. 05, 2007

Top Story

ARM Announces Development Kit To Reduce Time-To-Market Of Mobile Gaming Platforms

ARM today announced the ARM® Mali™ Software Development Kit (SDK), which enables game developers to quickly transition from generic application development to ready-to-use designs for a wide range of handsets. The Mali SDK enables developers to create and test games before silicon exists, thereby ensuring that new games are available on the day the handset is released and maximizing the time for which their games are marketable.

• Stretch Selects Tensilica Xtensa LX Processor and HiFi 2 Audio Engine to Power Second Generation S6000 Software Configurable Processor
• Lattice Announces LatticeECP2M FPGA Solution for PCI Express V1.1
• Virage Logic Expands in China with Distributor Relationships
• Faster verification is the goal at ST
• Ittiam Systems Selects Altera's Stratix II FPGAs for Multi-Format High-Definition Video Decoder Engine
• Stretch Unveils Second Generation Software Configurable Processor Architecture
• Faraday's Board Appointed John Hsuan as Chairman
• Imagination Technologies Shows Next Generation of Mobile Graphics Technologies at GDC 2007
• FSA Announces Danny Biran of Altera to Join Its Board of Directors
• Broadcom Demonstrates New 65 Nanometer Dual Advanced Video Decoder Chip
• IntellaSys Unveils Industry's First 128-Bit, Hardware-Encrypted Controller Chip for USB 2.0 NAND Flash Memory Used in Thumb Drives

Headlines for Friday Mar. 02, 2007

• New MOSIS Shared Wafer Service on IBM’s 130nm 8WL Process Makes High-Performance RF Chip Fabrication Affordable
• Imagination Technologies Opens Development Centre in Pune, India

Headlines for Thursday Mar. 01, 2007

Top Story

DOLPHIN Integration announces a new generation of Audio CODEC with embedded voltage regulator

Dolphin Integration has just released a Second Generation of audio CODECs offering a wide set of features and lowering integration costs. With an SNR at system-level measured at 90 dB, Dolphin's CODEC Best-in-class audio quality was already preferred by diverse Golden Ears finding it at par with the top external codec IC's

• Over 200 Million SoCs Now in Production Using Sonics SMART Interconnect Solutions
• Gaisler Research announces Linux 2.6 Symmetric Multiprocessing (SMP) support for the LEON3 processor
• IC Nexus and HDL Design House Teaming with Each Other to Offer Combined Broadest Portfolio of Services To Customers
• Carbon's Virtual Hardware Models Plug-and-Play With CoWare Platform Architect
• TES Announces Second Reference Platform For Gateway and Router Applications
• IPextreme and Freescale Webinar on ColdFire IP: Maximizing the Benefits From SOC Integration of the Popular Core