D&R Headline News (April 2007)

Headlines for Monday Apr. 30, 2007

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Semico: Opportunities Abound in the Structured ASIC Market

Revenue for the Structured ASIC category grew 20% in 2006 and is projected to increase 13% in 2007 according to Semico. Unit growth of the worldwide Structured ASIC market is forecasted at a CAGR of 28.2% in the years 2007 through 2011.

• First Quarter Global Chip Sales Grew by 3.2 Percent from 2006
• Hidden IP: booby trap or buried treasure?
• IRCONA Joins the Lattice Leader Design Services Program

Headlines for Friday Apr. 27, 2007

• Parrot Licenses ARM926EJ-S Processor
• Patriot Scientific CEO David Pohl to Retire

Headlines for Thursday Apr. 26, 2007

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Synopsys Releases Wireless USB WHCI Host and Dual-Role Device IP Based on the Certified Wireless USB Specification From USB-IF

Designed for applications like PC chipsets, set top boxes, personal video recorders, DVD Players and digital TVs, the DesignWare Wireless USB Host is based on the Wireless Host Controller Interface (WHCI) specification. Designing to the WHCI specification enables system makers to build applications on standard WHCI drivers to save months of software driver development.

• Inapac Technology Releases New 16Mb DRAM Design for Mobile Applications That Reduces SiP/MCP Cost
• ARM Holdings plc Reports Results For The First Quarter Ended 31 March 2007
• Hantro Pave's the Way for Microsoft Silverlight in Mobile
• CebaTech Announces CebaIP Platform for End-to-End Development of Data and Storage Networking ASICs or FPGAs
• Innovative Silicon Names Paul Pickering VP of Worldwide Sales
• Saifun Semiconductors Reports First Quarter 2007 Results
• QuickLogic Ships the First ArcticLink Solution Platform, with Fully Integrated USB 2.0 High Speed On-the-Go Controller and PHY
• TSMC Reports First Quarter EPS of NT$0.73
• Aloka Selects Xilinx EasyPath FPGAs for Diagnostic Ultrasound System
• MIPS Technologies Reports Third Quarter Fiscal 2007 Revenue; Update on Stock Option Investigation
• Rambus Reports First Quarter Revenue

Headlines for Wednesday Apr. 25, 2007

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Synopsys Enhances DesignWare Synthesizable IP for AMBA 2 and AMBA 3 AXI Protocols

The new release includes a new I2S protocol IP for the APB bus, an AXI-to-APB3 compliant bridge with built-in fabric, and a highly configurable AXI-to-AXI bridge supporting a multi-layered AXI bus-based design. The release also includes extensive enhancements to the existing IP for the AMBA 2 and AMBA 3 AXI protocols

• Silicon Hive spins out from Philips; New Venture Partners leads $10 million investment round, joined by TVM Capital and Philips
• Standards Support Pushes VaST's CoMET6 Deeper Into Embedded Supply Chain
• Xelic Announces Immediate Availability of 10Gb/s Ethernet Rate Adaptation IP Core
• Sonics and Denali Team on Platform Approach for Consumer SoC Designs
• Patriot Scientific Reports Favorable Fiscal Q3 Net Income of $9.6M, or $0.02 Diluted EPS

Headlines for Tuesday Apr. 24, 2007

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Renesas Technology Releases The Software Development Kit for Bluetooth Audio Products

Renesas Technology today announced the development of the SOUNDabout Suite as a software development kit (SDK) for microprocessors incorporating a 32-bit SuperH Family SH-4A, SH-2A, or SH3-DSP CPU core, for the development of high-sound-quality audio products using Bluetooth wireless communication technology.

• Actel Announces First Quarter 2007 Revenues
• LogicVision Reports First Quarter 2007 Financial Results
• EVE Unleashes Next-Generation Hardware Accelerator Designed for Ease of Use, Offering Close to Unlimited Capacity
• DSP Chip Market Is Forecast to Grow a Moderate 8% In 2007, According To New Forward Concepts Study

Headlines for Monday Apr. 23, 2007

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IP providers cast wary eye on TSMC

TSMC is quietly but aggressively laboring to broaden its portfolios of internally developed semiconductor intellectual property and ''proven'' third-party IP. That has some observers asking whether the company is migrating to a more ASIC-like business model--and whether third-party IP vendors should be concerned about the foundry giant's competitive ambitions.

• Impinj's AEON/MTP Logic Nonvolatile Memory IP Earns TSMC Quality Certification
• S1 Core, a 64-bit Wishbone-compliant CPU Core based upon the OpenSPARC T1 microprocessor, easily synthesized for Virtex-4
• IC Manage Announces Global Design Platform (GDP) for Scalable, Collaborative IC Design
• Entropic Marks Milestone with Shipment of Five Millionth MIPS-Based Coax Network Chipset
• Wintegra Launches Market Leading Silicon and Software Solution for Mobile WiMAX Basestations
• GateRocket Delivers the EDA Industry's First Device Native Verification Solution for Advanced FPGAs

Headlines for Friday Apr. 20, 2007

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Global Unichip Completes First Successful 65nm Tape-Out in Taiwan

This successful tape-out marks the first of four 65 nm tape-outs planned by GUC in the first half of 2007. The company is also planningtwo testchip tape-outs in 45nm before the end of 2007. Additionally, projects using GUC's 90nm process will begin mass production later this year.

• A panel discusses 65-nm mixed-signal design
• ARM Appoints Anil Gupta as Managing Director, India Operations
• Xilinx and port GMBH Demonstrate Industry's First Complete Solution for Ethernet Powerlink

Headlines for Thursday Apr. 19, 2007

• MoSys and BiTMICRO Networks Sign Agreement for High-Performance 1T-SRAM(R) Memory Macro Geared for Family of Portable E-Disk Storage Solutions
• Dramatic Area and Power Saving, Faraday miniLib Adopted by Afatech for Digital TV IC Designs
• Evatronix announces the C1394A Software Stack supporting the IEEE1394a standard
• TI Makes ZigBee Available for Mass Market with Free Software Stack

Headlines for Wednesday Apr. 18, 2007

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Cavendish Kinetics Announces National Semiconductor Adopts its Nanomech Technology

Cavendish Kinetics, a fabless semiconductor IP company, announced today that National Semiconductor Corporation is working with the company to qualify its Nanomech(tm) embedded non-volatile memory technology for National's key analog and mixed signal processes.

• Satin IP Technologies committed to IP Reusability through the launch of VIP Lane, innovative Design-for-Reuse software cockpit
• Altera Announces FPGA-Based Accelerator Support for Intel Front Side Bus
• Magillem Design Services introduces MAGILLEM 4.0, the most comprehensive Integrated Design Environment based on the IP-XACT standards by The SPIRIT Consortium
• Jetstream Media Technologies' New Real-Time Video Effect IP Core Delivers Easy to Use, Fun and Personalized Memories

Headlines for Tuesday Apr. 17, 2007

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Intel System-On-A-Chip Media Processor Powers New Generation Of Consumer Electronics Devices

The Intel® CE 2110 Media Processor is a complete system-on-a-chip (SoC) architecture that combines a 1GHz processing core with powerful A/V processing and graphics, and I/O components, onto a single chip.

• Elliptic Extends Industry Leadership in NIST Validation
• Rambus and TES Electronic Solutions Sign Joint Marketing Agreement
• Mercury Computer Systems Announces Collaboration with NTT-AT for a Cell BE Processor-Based Solution for AVC/H.264 Codec
• Xilinx and 4i2i demonstrate H.264 HD encoder and decoder with streaming over RTP
• TOPPERS-Pro, the First Commercial Real-Time Operating System for Altera Nios II Multiprocessor Designs
• Mixel Announces the Availability of Its 4.25 Gbps High Performance, Highly Programmable, SerDes IP's Characterization Report
• Handshake Solutions releases clockless interconnect IP
• Tensilica Adds Support for Low-Cost, Hardware-Based Simulations of Diamond Standard Processors
• JMicron relies upon nSys again for PCI Express Gen2 Verification IP
• Hua Hong NEC Establishes NVM Technical Cooperation Relationship with Cypress
• MIPS and Texas Instruments Get Behind The SPIRIT Consortium with Dedicated Engineering Support
• SystemC and ESL in 2007: Everyone's Talking the Same Language

Headlines for Monday Apr. 16, 2007

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Broadcom Standardizes on ARC's Configurable Technology for High Volume Multimedia Applications

Broadcom Corporation Extends Existing ARC Relationship with New 10 Year Licensing Agreement

• MIPS64 Architecture Licensed by NEC Electronics for Next-Generation VR Series Processor Core
• Denali Launches New Product to Speed System-On-Chip Verification
• Lattice Releases Reference Design For GPON Burst Mode Receiver
• Xilinx and Image Processing Techniques Announce New Advanced Video Development Platform
• ARC Building Advanced CPF-Enabled Flow to Lower Power Consumption of its Configurable Subsystems and Cores
• E2v Chooses 32-bit Processor for Upcoming Products: the Cortus APS3 Core from CAST
• CAST Expands Image Compression Line with New JPEG-LS Encoder Core
• Silistix Hires Interconnect Industry Veteran David Lautzenheiser as Marketing VP
• Xilinx Introduces Dual Link HD-SDI and 3G-SDI Reference Designs on Industry's First Interoperability Platform
• Harris Chooses Altera Stratix II GX FPGAs for New Multi-Format Broadcast Router Line
• Evatronix Demonstrates Transactional Model of USBHS-OTG Controller
• Cosmic Circuits announces tie-up with SUPERTEC of Israel
• Mentor Graphics Launches Veloce Product Family Delivering Industry's Fastest Functional Verification Platform
• Xilinx Announces FPGA-Based Deserializer Solution for TI's ADS60000 ADC Family
• Xilinx Announces New MultiChannel Video-Over-IP Solution

Headlines for Friday Apr. 13, 2007

• LogicVision Receives Letter from Nasdaq Regarding Noncompliance with Minimum Bid Price Rule
• Chartered Realigns Senior Management Roles to Lead Next Phase of Growth
• Imagination Technologies Group plc -- Trading Update
• Dongbu Electronics Leads Foundry Industry in Development of Image Signal Processor (ISP) Design Library
• Commentary: ESL should drive emulation

Headlines for Thursday Apr. 12, 2007

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Vector Capital Completes Acquisition of SafeNet, Inc.

Vector Capital today announced that it has completed the acquisition of SafeNet in a transaction valued at approximately $634 million. The two-step acquisition consisted of a tender offer by Stealth Acquisition Corp., an affiliate of Vector, for all outstanding shares of SafeNet, Inc. into which more than 83% of the outstanding common shares of the Company were tendered and not withdrawn, followed by a merger of Stealth Acquisition Corp. with and into SafeNet.

• Patriot Scientific Confirms Continuing Momentum as Sharp Purchases Moore Microprocessor Patent Portfolio License
• ChipX Appoints Michael Brown as Vice President of Worldwide Sales

Headlines for Wednesday Apr. 11, 2007

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GDA Technologies Selected by Renesas Technology for PCI Express to AMBA AXI Bridge

The PCI Express-AMBA Bridge (PAB) is a highly flexible and configurable design with a PCI Express interface on one side and an AMBA interface on the other. The Bridge architecture is such to facilitate interface with a PCI Express controller used as end-point, or root-complex.

• Tower Semiconductor and Paragon Communications Jointly Announce Development Completion of XNN-Based Power Amplifier Booster
• CAST Selects Avery Design Systems for PCI Express Verification IP
• Gaisler Research Announces ThreadX RTOS Support for the LEON processor
• Jazz Semiconductor Announces 0.13-micron SiGe BiCMOS Process Designed for High Speed Wireless and Optical Communications Applications

Headlines for Tuesday Apr. 10, 2007

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MOSAID Delivers Silicon-Proven PLLs at 65 Nanometers

MOSAID's fractional-N PLL is a fully integrated, programmable, low-power, high-performance Delta-Sigma, Fractional-N product. It is optimized for line-operated and battery powered applications at system clock rates as high as 3.2GHz. The large fractional multiplication range of MOSAID's PLL enables it to address many markets and applications with a single, low-cost crystal frequency, thus reducing inventory, delivery time and bill of materials (BOM) cost.

• OCP-IP Standardizes on Synopsys' DesignWare Verification IP for OCP-IP's CoreCreator Verification Toolset
• Virage Logic Named as TSMC's 45-Nanometer Process Early Development IP Partner
• Clear Shape and Lightspeed Logic Collaborate to Improve Manufacturability of Mask Reconfigurable IP
• Mentor Graphics Nucleus USB Software Receives High-Speed, On-The-Go Certification
• Uniquify Releases Industry's First Smart DDR Memory Controllers
• TEMENTO SYSTEMS announces the introduction of a Bus Trace Analyzer for On-Chip AMBA and ARM processor-based Verification
• MoSys Technology Featured in Mobile Phone Application Processor Through Progate-Designed Chip
• TSMC March 2007 Sales Report
• Focus Enhancements Completes Tape-Out of UWB Digital Chip Designed for Wireless USB Applications
• MPEG LA Sues DVD Video Disc Manufacturer Regency Media Pty Ltd., of Australia for Breach of MPEG-2 License Agreement

Headlines for Monday Apr. 09, 2007

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VSIA Announces Release of QIP Metric Now Publicly Available with Hard IP Extension

QIP Version 3.0 includes enhanced support for hard IP quality metrics, including support for different types of hard IP, hierarchical evaluation and graphical results representations, and many automated features that are new to this version. Included in this release is the verification IP extension which includes Quality metrics for drivers and responders, monitors, bus functional models and stimuli generators.

• MIPS Technologies and Trident Microsystems Complete Licensing Agreement for MIPS32 24KEc Pro Core
• Open-Silicon Introduces Multi-Layer Mask Program: Reduces Mask Costs by up to 50% for 90nm and Smaller Lithographies
• MOSAID Names New CEO and New Chairman of the Board
• Atmel Licenses ARM1176JZF-S Processor
• VinChip Systems announces USB PHY Verification Services
• TSMC Expects to Enter 45nm Production in September
• DOLPHIN Integration supports Lynguent for excellence in AMS modeling
• Altera FPGA Replaces 64 DSP Devices in Fairlight's New Media Processing Engine

Headlines for Friday Apr. 06, 2007

• ARM announces its unaudited financial results to 31 December 2006

Headlines for Thursday Apr. 05, 2007

Top Story

S3 Mixed Signal IP Portfolio Tapes Out at 65nm

S3 (Silicon and Software Systems) today announced the tape-out at 65nm of its high-performance mixed signal IP portfolio for wireless and consumer applications. S3 has already achieved multiple volume engagements with its first-time right silicon at 90nm, enabling rapid time to production revenue for its global client base.

• Impinj First and Only Provider of One-Time- and Multiple-Time-Programmable Nonvolatile Memory Cores in 90-nanometer Logic CMOS
• TranSwitch Announces Optimized Ethernet Gigabit PHY IP Core
• Virage Logic First Semiconductor IP Vendor With Silicon Proven Memory on TSMC's 65nm GP Process
• Comsis and Gaisler Research AB signs license agreement for LEON3
• MoSys Boosts Global Sales Presence With New Japan Country Manager
• Arasan Chip Systems Updates AC2200ie SDIO Card Controller ASIC Software
• Gartner's Final Semiconductor Market Share Results Show Industry Grew 10 Percent in 2006
• Not everyone gets mugged for IP
• ESC video special: Xilinx talks programmable logic

Headlines for Wednesday Apr. 04, 2007

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Ittiam Systems Gets the Coveted 'Wi-Fi CERTIFIED(TM)' for its 802.11g IP

Ittiam Systems today announced that it has achieved the most well known ''Wi-Fi Certification'' from the Wi-Fi Alliance(R) for IEEE 802.11b, IEEE 802.11g, WPA(TM), WPA2(TM) and EAP for its WLAN IP.

• MIPS Technologies Announces Preliminary Fiscal Third Quarter Revenue Results
• ON DEMAND Microelectronics Selects Denali's Mobile DDR Memory System Solution for Latest Video Portable Devices
• VSIA Works with Hong Kong to Extend QIP Metric
• eSilicon Optimizes Arm Processor For TAK IMAGING
• Faraday Monthly Sales Report -- March 2007
• Luminary Micro Announces Motion Control Reference Design Kits for Stellaris Microcontrollers Based on ARM Cortex-M3

Headlines for Tuesday Apr. 03, 2007

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MindTree Consulting Announces ''UltraWiz'' range of UWB IP's

MindTree's ''UltraWiz'' UWB MAC silicon IP is based on the WiMedia MAC 1.0 specification and MAC-PHY interface specification V1.2 and has been validated on FPGA platform. The ''UltraWiz'' IP meets all mandatory and optional features and is ready for integration in a SOC platform. In addition, MindTree offers complementary test tool ''UTest'' for validation and testing of all mandatory and advanced features.

• Altera's Triple-Speed Ethernet MegaCore Function Successfully Completes UNH-IOL Conformance Testing
• Altera's Nios II Processor Supported by Vector Informatik's OSEK/VDX-Compliant RTOS for Automotive Applications
• RFEL's Mixed Radix cores, adaptable for next generation 3GPP LTE base station applications
• ARM and Synplicity Announce Marketing and Collaboration Agreement for Cortex-M1 Processor
• ARC Signs $15M Multiyear License With One of the Largest Consumer Electronics Companies
• AnaFocus Chooses Altera's Embedded Solutions for Single-Chip Vision System
• CMC Microsystems Provides Hundreds of Canadian University Researchers with Access to Tensilica Prototyping Technology for Designs Using Xtensa LX2 Configurable Processors
• Fred N. Lancia Appointed Vice President of Sales for eASIC

Headlines for Monday Apr. 02, 2007

Top Story

Freescale Opens Licensing of Power Architecture(TM) e200 Core Family Through IPextreme

Extending the reach of Power Architecture(TM) technology in the embedded market, Freescale Semiconductor is licensing its e200 core family to designers of system-on-chip (SoC) devices and application-specific semiconductor products (ASSPs). Freescale will license its e200 cores through an agreement with semiconductor intellectual property (IP) licensing specialist IPextreme Inc.

• Transmeta Files 2006 Annual Report With SEC and Provides Progress Update on 2007 Restructuring Plan
• Oki starts 'fab lite' trend in Japan
• Faraday Implements Ultra Small ARM926EJ-S Hard Core in UMC 0.13um Process
• ARM Announces RealView Development Suite 3.1 For Low-Risk Embedded System Software Development
• Xilinx Launches New Low-Cost Spartan-DSP Series
• ARC Acquires Teja Technologies To Create Software Platforms and Development Environments For the VRaptor Multicore Architecture
• ARC Announces Strategic Organizational Changes: Appoints Meyer to COO, Establishes ''Office of the CTO''
• CoWare Virtual Platforms Transform Enterprise Go-to-Market Strategies and Software Development Methodologies
• Exec Q&A: TI's DSP, ASIC chief
• Atmel Introduces the World's Lowest Power 32-bit Flash MCU With Ethernet and USB On-the-Go
• Express Logic's ThreadX RTOS Supports AMCC's PowerPC 405EZ Acadia Evaluation Kit
• CSR's BlueCore5-Multimedia now available with Aurisound's Adaptive Focus-Beam noise cancellation technology