D&R Headline News (May 2007)

Headlines for Thursday May. 31, 2007

Top Story

CEVA Announces Next Generation CEVA-TeakLite-III DSP Architecture Featuring Native 32-Bit Processing

Targeting next-generation Hi-Fi audio applications, the CEVA-TeakLite-III inherently supports 32-bit data processing functions with multiple precision points and offers an enlarged 64-bit data memory bandwidth. A FFT accelerator further boosts audio performance and reduces power consumption. For example, a 7.1 channel Dolby Digital Plus decoder would consume only 15% of the core's available MHz at a 90nm process, compared to 47% for its predecessor, the CEVA-TeakLite.

• Rambus Receives Exception from Nasdaq Listing and Hearing Review Council
• SiRF GPS IP Powers New Renesas Automotive System on Chip
• Sonics and Synopsys Collaborate to Significantly Improve SoC SDRAM Memory Subsystem Performance
• Cadence and Denali Team Up to Enable Advanced DDR-PHY Methodology
• Denali and Mentor Team Up to Enable Verification IP for SystemVerilog Verification Environments
• HARDI Electronics teams with LSI to offer SerDes for ASIC Prototyping
• Chartered and Mentor Graphics Team to Offer Technology Design Kits for 65 and 90 Nanometer Common Platform Technology Processes
• Certicom Files Suit Against Sony For Patent Infringement
• Inapac Technology and ProMOS to Collaborate On 256Mb Mobile DDR DRAM for System-in-Package / Multi-Chip Package Applications

Headlines for Wednesday May. 30, 2007

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Synopsys Announces the Industry's First Comprehensive SATA AHCI IP Solution

The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems.

• EVE's ZeBu Proven High-Speed Verification Solution for IBM PowerPC 405, 440 SoC Designs
• Analysis: BDTI releases ARM Cortex-A8 benchmarks
• Arithmatica Appoints New CEO
• Xilinx Announces Virtex-5 System Monitor System Management Solutions

Headlines for Tuesday May. 29, 2007

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Silicon Image Intellectual Property Business Expands: HDMI Core IP Paired with PHY Semiconductors Solidifies Silicon Image's Industry Leadership

Silicon Image today announced that by combining its digital implementations of the HDMI IP cores with its HDMI analog physical layer (PHY) semiconductors, the company has begun to achieve significant market success, having already sold approximately four million HDMI PHY semiconductors.

• Denali Announces Databahn DDR3 Memory Controller IP Product
• Freescale Selects Denali for DDR Memory System Deployment
• Ceroma Selects Silicon Image's Multistandard Video Decoder IP Core for Its Full High-Definition Capable DTV Chip
• LG and ARM Develop New Digital-To-Analog Converter Technology For US 2009 TV Switchover
• ASIC IP Announces Availability of its Serial ATA Controller Core
• Commsonic pushes IP in China
• Gaisler Research extends the GRLIB IP library with USB 2.0 Host Controller
• Synopsys and ARM Optimize Reference Methodology for Aggressive Power Management
• Lattice Semiconductor Announces Industry's First True 90nm Non-volatile FPGA Family
• Renesas and VaST Strike Global Partnership Addressing Automotive Software Development

Headlines for Monday May. 28, 2007

Top Story

PLDA Announces the Industry's First True Look at PCIe Gen 2

The PLDA PCIe Gen 2 demo will include a FPGA-based board running PLDA's PCIe Gen 2 XpressRich IP on a server Platform featuring two quad processors from the industry leading processor manufacturer.

• Legend releases Turbo-MSIM Fast-SPICE Simulator for Verification, Analysis and Characterization in SoC Design

Headlines for Friday May. 25, 2007

Top Story

Mentor Graphics Introduces Smallest Footprint, Industry-Compliant Serial ATA PHY for Optimized Low-Power Designs

The SATA PHY IP core, targeted for the TSMC 130nm Low Voltage Oxide (LVOD) process, provides a completely integrated solution for both SATA host and device applications running at either 1.5Gbps or 3.0Gbps speeds.

• Sonics and JEDA Technologies Deliver ESL Validation
• Dolphin Integration launches a standard cell library with ultra-high density up to 30% savings
• Infineon Relies On DAFCA for Post-Silicon Validation

Headlines for Thursday May. 24, 2007

Top Story

Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies

Implemented in the 65-nanometer (nm) Common Platform process, Synopsys' DesignWare PHY for PCI Express and digital controllers are the first 65-nm IP to pass the PCI Express 1.1 compliance testing by the PCI-Special Interest Group (PCI-SIG(R)). Additionally, Synopsys' DesignWare USB 2.0 nanoPHY IP in the Common Platform 90-nm process is the first implementation to have earned Hi-Speed USB 'On-the-Go' (OTG) logo-certification by the USB Implementers Forum for devices manufactured at multiple foundries using a single GDSII source.

• ARM shows royalties leveling off around 10 cents per handset
• Imagination Technologies Group plc - Preliminary results for the twelve months to 31 March 2007
• Avery Design Systems Announces Support for PCI Express IO Virtualization and AMBA AXI
• Xilinx Virtex-5 SXT FPGAs Achieve PCI Express v1.1 Compliance
• STMicroelectronics Announces Ultra-Low-Cost Development Kit for STR9 ARM966E Core-based MCUs with Ethernet Connectivity
• Stream Processors Delivers Industry's Highest-Performing Digital Signal Processor
• TechnoConcepts, Inc. Announces True Software Radio Test Chips in CMOS 90 nm, a Key Milestone for Reconfigurable Chip

Headlines for Wednesday May. 23, 2007

Top Story

Leading Fabless IC Company Chooses PLDA PCIe Gen II Solution for Their Next Generation 65nm Products

The PCI Express Generation II product from PLDA features double the transfer speed – up to 5Gb/s – while maintaining the same quality, backward-compatibility, and ease of integration inherent in PLDA's PCI Express products. A complete test chip for PLDA's Generation II IP will be available to third parties beginning Q1 2008.

• Broadcom to Bring ARM Cortex-A8 to Powerful VideoCore Mobile Media Product Line
• Infineon, IBM, Chartered, Samsung, Freescale Expand Technology Agreements - Alliance Partners Will Collaborate to Develop and Manufacture Advanced 32-Nanometer Semiconductors
• MoSys Licenses 1T-SRAM for Advanced 55NM Process Technology to NEC Electronics
• FS2 Introduces System Navigator Tools for MIPS32 74K Core Debug
• Renesas Introduces Faster (600MHz) 32-bit SoC Device With Performance and Enhanced Peripherals Needed for Next-Generation Car Navigation Systems

Headlines for Tuesday May. 22, 2007

Top Story

Intel , STMicroelectronics and Francisco Partners Establish a New Leader in Flash Memory

STMicroelectronics, Intel and Francisco Partners today announced they have entered into a definitive agreement to create a new independent semiconductor company from the key assets of businesses which last year generated approximately $3.6 billion in combined annual revenue.

• AMD Chooses TSMC 65nm Process for GPU Product Line
• MOSAID Introduces Industry's First Double Data Rate (DDR) SDRAM Physical Interface (PHY) Compiler
• eASIC and IAR Systems Deliver e926 Development Kit for Designing Low-Cost, Customized ARM926EJTM Embedded Systems
• Novelics Announces MemQuest, a Suite of Memory Compilers Built on a Common Platform that Concurrently Excels in Active Power, Leakage Current, Speed, Portability, and Cost
• Imagination Technologies' PowerVR MBX Graphics Accelerator Technology Used in Freescale's MPC5121e Processor
• CAST Releases DSP Coprocessor for Cortus APS 32-bit Processor Cores
• MIPS Technologies Unveils Industry's First Fully Synthesizable Processors to Surpass 1 GHz; Broadcom Takes Early License
• On2 Technologies Announces Acquisition of Hantro Products, a Leader in Embedded Video Technology
• Yogitech Selects Mentor Graphics' Platform Express to Deliver IP-XACT Descriptions for Merchant IP Products

Headlines for Monday May. 21, 2007

Top Story

Silistix CHAINarchitect Bridges Gap Between Conventional and Leading-Edge Interconnect Methodologies

With CHAINarchitect, chip architects can easily explore new interconnect topologies and perform ''what if'' analyses to optimize on-chip communications (bandwidth and latency) between IP cores along with overall system characteristics such as power, die area, system-level performance and others.

• Fujitsu Announces Mobile WiMAX SoC Performance and Delivery Schedule
• The SPIRIT Consortium Accepts SystemRDL Donation from Denali
• Broadcom Licenses ARM Cortex-M3 Processor For Next-Generation Wireless Applications
• Denali and LeCroy Demonstrate Industry-Leading PCIe 2.0 Solutions at PCI-SIG Developers' Conference
• Atmel Launches Customizable Microcontroller-based SoC Platform
• Jasper Electronics Leverages Actel Fusion Reference Platform to Rapidly Deploy MicroTCA Power Module
• AMCC Announces Titan: 2 GHz Power Architecture Processor for Embedded Applications
• Freescale Unveils Versatile Multi-Core Processor for Telematics, Consumer and Industrial Applications
• Texas Instruments and NSCC Deliver the Industry's First Single-Chip AVS IPTV Set Top Box Based on DaVinci(TM) Solution
• Cavendish Kinetics Announces National Semiconductor Adopts its Nanomech Technology

Headlines for Friday May. 18, 2007

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Algotronix to demonstrate its DesignTag Electronic IP labelling technology at the 44th DAC in San Diego

Based on cryptographic research into ''side channels'' DesignTag is a small, low power, active digital circuit supplied as an IP core for inclusion in larger designs. The presence of DesignTags can be detected by a sensor placed in contact with the package of the chip which contains them. DesignTag communicates a unique tag to the sensor which can then be used to access information on the tagged product in a web-based database.

• Memory IP Characterization for 45nm Technology and below

Headlines for Thursday May. 17, 2007

Top Story

Denali Announces Availability of PCI Express I/O Virtualization Solutions

Denali's Databahn PCIe IOV cores and PureSpec PCIe verification IP products provide full support of the Address Translation Service specification, Single-Root I/O Virtualization specification, including physical and virtual function (VF) configuration spaces, VF Alternate Routing-ID, and Functional Level Reset (FLR) capabilities.

• Synopsys Switch IP for PCI Express Passes PCI-SIG Compliance Testing
• Phoenix Microelectronics Licenses ARM7TDMI Processor For Megaflash SIM Card SoC
• Wi-LAN Acquires Key Communications Patent
• Flowgic selects Ethernet nVS (nSys Verification Suite) Verification IP
• Duolog Technologies announces the release of BitWise, its powerful SPIRIT compliant register management tool
• CriticalBlue Announces Multicore Methodology for Single Threaded Software

Headlines for Wednesday May. 16, 2007

Top Story

BroadLight Continues 3rd Generation of PON System Deployment Success With Denali DDR Memory System Solution

Denali's Databahn solutions aid BroadLight's developers to quickly design and verify DDR memory systems that meet or exceed OEM high-speed PON design requirements and time-to-market windows.

• Wi-LAN Announces the Addition of Paul Richman and Rick Shorkey to its Board of Directors
• Tensilica Announces Industry's First MP3 Decoder Under 6 MHz
• Rambus Receives NASDAQ Notice of Non-Compliance
• MIPS Technologies Receives Additional Notice from NASDAQ

Headlines for Tuesday May. 15, 2007

Top Story

Synopsys Unveils Industry's First Certified Hi-Speed USB 'On-the-Go' nanoPHY IP for TSMC'S 65-Nanometer Process

Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the TSMC 65-nm process nodes, uses half the power and die area compared to previous USB solutions and enables faster time-to-market and reduced risk.

• MOSAID Announces Three Senior Appointments
• Cebatech Announces GZIP Family of CebaIP Cores for Efficient High Speed Compression and Decompression inside Data and Storage Networking ASICs and FPGAs
• Faraday Introduces Repairable Memory Development System - REMEDE
• Cadence Selects Wipro-NewLogic's Wireless LAN IP for its Low-Power Methodology Kit
• austriamicrosystems expands non-volatile memory portfolio with ultra high reliability EEPROM block
• Xilinx 65nm Virtex-5 LX Selected for Hitachi Kokusai Electric Industrial Cameras
• ChipVision breakthrough ESL technology enables interactive creation of RTL code optimized for low-power consumption

Headlines for Monday May. 14, 2007

Top Story

OneSpin Enhanced 360 Module Verifier Delivers Industry's Firt Complete Multi-Configuration IP Verification Solution

The enhanced 360 MV supports the verification of IP with configurable functionality, such as optional memory-management units, or configurable synchronous or asynchronous FIFO implementations, and configurable dimensions, such as configurable bus-widths, FIFO depths, or register counts

• CoWare Virtual Platform Product Family Adopted by Fujitsu For Completing Their Next-Generation SoC Design Flow
• Microtronix premieres this summers' Full HDTV ''Streaming'' Blockbuster Hit
• KPIT Cummins develops AUTOSAR 2.0 Compliant MCAL Layer and ECU Abstraction Layer
• InterDigital Licenses CEVA-TeakLite DSP Core for Multi-mode Baseband Platform IP
• Evatronix adds the USB On-The-Go Software Stack to its USB solutions portfolio
• Gaisler Research announces new licensing agreements with leading European companies
• eASIC Partners with Premier Technical Sales to Enhance its Customer Sales and Support for Nextreme Structured ASIC in North America
• Cadence Speeds Adoption of Wireless and Consumer Low-power Designs with Low-power Methodology Kit
• TI takes two approaches to IC manufacturing
• Comsys ComMAX Mobile WiMAX Processors to Power dmedia Advanced Personal Navigation Devices
• License-free, FPGA-based Single Chip Controller for Low Cost SERCOS III I/Os available
• Leading Semiconductor Companies in China Adopt the VMM Verification Methodology

Headlines for Friday May. 11, 2007

• Cosmic Circuits and SINOSTAR partner for Analog IP in China
• Wi-LAN Signs Definitive Agreement to Acquire Tri-Vision
• GDA Collaborates With AMD to Develop Home Cinema Design
• Dongbu HiTek Adds ARM926EJ-S Processor to Intellectual Property Portfolio in Support of System-on-Chip Designs
• Wi-LAN Acquires OFDM Patents from Bristol University
• Transmeta Reports First Quarter 2007 Results

Headlines for Thursday May. 10, 2007

Top Story

Duolog Technologies tapes out IEEE 802.15.4/Zigbee radio which offers significant time to market reductions for semiconductor customers

Duolog Technologies today announced the tape-out of a 0.13um IEEE 802.15.4/Zigbee radio test chip as part of their 802.15.4 transceiver development program.

• Commentary: ANSI C won't work for ESL
• Arasan Chip Systems Releases a SDIO neX Software Stack to Optimize Performance and Reliability
• Tata Elxsi Adopts SonicsMX SMART Interconnect Solution for Its Digital Media Solutions Platform
• TSMC April 2007 Sales Report
• ChipX Partners with Beyond Semiconductor to Offer 32 bit Processors
• Cadence Extends Verification Resources With New Plan-to-closure Methodology Qualified Program

Headlines for Wednesday May. 09, 2007

Top Story

Lightspeed Logic Introduces Reconfigurable Logic for TSMC 90nm with ARM Standard Cell Libraries

Lightspeed Logic's Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80% the density of traditional methodologies for multi-million gate logic blocks, twice the density of competing mask reconfigurable solutions.

• Intrinsity's FastCore(TM) Embedded ARM, MIPS and PowerPC Cores Offer 2 to 4X Better Performance
• Silicon Hive Announces HiveFlex VSP2200 Series Processor Cores for HD Video Signal Processing
• Mercury Computer Systems Provides Silicon IP to Raytheon for its MONARCH Programmable ''Supercomputer on a Chip''
• Ellipsys 2.0 Software Released by Elliptic - features Support for Elliptic Curve Cryptography & RSA Security
• VeriSilicon Announces Agreement with IBM to Dramatically Reduce Design Time for PowerPC Based Products
• VeriSilicon and ARM Extend Partnership to Further Address Advanced Consumer and Networking SoC Designs
• ARM Java and Graphics Acceleration Technology Licenses to be Transferred to Sun Microsystems via Acquisition of SavaJE Technologies
• K-micro Runs Digital TV Devices on TSMC 90nm Embedded RAM
• DOLPHIN Integration releases a ROM in 65 nm with Ultra high density and ultra low leakage
• Silicon Interfaces announces the release of its new RapidIO Physical Layer Interface OpenVera Verification IP

Headlines for Tuesday May. 08, 2007

Top Story

MOSAID and LSI Sign Exclusive Patent Licensing Agreement

Effective immediately, MOSAID has the exclusive right to sub-license more than 50 LSI patents relating to memories, digital signal processors (DSPs), microprocessors, application specific integrated circuits (ASICs), and semiconductor processing technology.

• LEON3-FT-RTAX used as instrument controller in the BepiColombo satellite
• New ARM Jazelle Technology Software Raises the Performance Bar of Mobile Multimedia Applications Using Java
• SRS Labs Ports TruSurround HD to Tensilica's HiFi 2 Audio Engine for HDTV SOC Designs
• Faraday Partners with eSOL to Support µITRON for its ARM CPU
• Xilinx Announces Production Qualification of Entire Line of Spartan-3A I/O Optimized FPGAs
• TSMC Board Approves Expansion of 45 Nanometer Capacity
• Mentor Graphics Delivers Enhanced 0-In Clock Domain Crossing and Formal Verification Technology

Headlines for Monday May. 07, 2007

Top Story

MOSAID Introduces Breakthrough Flash Memory Architecture

HLNAND Flash is a high-performance solution that combines MOSAID's own HyperLink memory technology with industry standard NAND Flash cell technology to deliver the industry's most advanced feature set, reaching sustained I/O bandwidths more than ten times higher than conventional Flash

• Bluespec Adds System-Level Building Blocks to AzureIP Foundation Library
• UMC targets CPUs, mulls commodity flash
• Faraday Monthly Sales Report -- April 2007
• Open-Silicon Inc. Acquires IP Assets of Zenasis Technology
• Dongbu HiTek adopts Legend Design Technology's Memory Characterization Tools for Quality Timing and Power Models
• Conexant Delivers World's First System-on-Chips for Fiber Optic Gateways
• Bluespec, EVE Create Platform for ESL Verification, Modeling, Architectural Design
• Certess Launches Certitude, First Product to Enable the Functional Qualification of Electronic Designs

Headlines for Friday May. 04, 2007

• Wi-LAN Strengthens Management Team
• Patriot Scientific Announces Nokia Purchase of Moore Microprocessor Patent Portfolio License
• Commetrex and Tensilica Announce Commetrex Fax Solutions for Tensilica's Processor Cores
• Aware, Inc. Reports First Quarter 2007 Financial Results

Headlines for Thursday May. 03, 2007

Top Story

EETimes Blog: Garage IP operation? Forget it!

Engineers who are thinking of launching a silicon intellectual property (IP) business in their garage with a couple of friends had better think again, according to panelists at this week's EDA Consortium meeting. The overall message: it's a big business for big players now.

• ARM First to License OpenGL ES 2.0 Benchmarks From Futuremark
• CSR launches BlueVOX Flash, the only fully flexible, reprogrammable solution for low cost headsets
• TI and Ittiam Ease Video Development with Availability and Support of Advanced Codecs
• Panelists cite pitfalls of silicon IP business
• Supreme Court ruling fallout: fewer patents, more litigation?
• Virage Logic Reports Second-Quarter Fiscal 2007 Results

Headlines for Wednesday May. 02, 2007

Top Story

STMicroelectronics Samples 65nm Multi-Standard Hard Disk Drive Physical Layer IP

STMicroelectronics today revealed the industry's first successful fabrication of the next- generation 65nm serial-interface MIPHY (Multi Interface PHY) Physical Layer interface IP (Intellectual Property). ST designed the macro-cell to be integrated with other functions into low power System-on-Chip (SoC) devices supporting both 3 Gbps and 6 Gbps Serial ATA (SATA) hard disk drives (HDDs) for mobile and desktop computing applications.

• FSA Announces Availability of Hard IP Quality Risk Assessment Tool Version 2.0
• NetXen Deploys Denali's PCI Express Verification IP for High-Performance 10-Gigabit Ethernet Enterprise Network Cards
• Coresonic strengthens board of directors; Successful technology entrepreneurs Tim Unger and Alain Fanet are nominated to Coresonic's board of directors
• Xilinx QPro Radiation-Tolerant FPGAs Enable ITT Cross-Track Infrared Sounder Program
• Wi-LAN Comments on Recent Market Activity

Headlines for Tuesday May. 01, 2007

Top Story

Future Waves Licenses Imagination Technologies' Broadcast Receiver IP Platform

Future Waves will market SoCs integrating Imagination's IP alongside Future Waves' leading multi-standard RF technologies to enable a range of mobile broadcast devices.

• The IP highway: Intellectual property licensing offers OEMs and semiconductor companies a new model for designing automotive electronics
• MoSys, Inc. Reports First Quarter 2007 Financial Results
• MoreThanIP First to Demonstrate 2.5 Gigabit Interoperability with Broadcom Switch
• Tensilica Offers Dolby Digital Plus 7.1-Channel Decoder for HD DVD Players, Blu-ray Disc Players, and Set-Top Boxes
• CEVA, Inc. Reports First Quarter 2007 Financial Results
• MOSAID Names New Chief Financial Officer