D&R Headline News (June 2007)

Headlines for Friday Jun. 29, 2007

Top Story

Infineon Achieves New Data Rate Breakthrough With 3.0 Gb/s Advanced Hard Disk Drive Read Channel and 6 Gb/s Serdes Interface

Infineon Technologies AG today announced it has demonstrated functionality and data rates exceeding 3.0 Gb/s speed of read channel, setting the pace for next-generation hard disk drive (HDD) System-on-Chip (SoC) technology

• MOSAID Announces Fourth Quarter and Year-End Results for Fiscal 2007 and Dividend
• Aniotek Selects ChipX Structured ASIC for Fieldbus Controller
• Beach Solutions Ensures Higher Quality IP with Metric Driven Tool

Headlines for Thursday Jun. 28, 2007

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Synopsys Teams With UMC to Port Mixed-Signal Connectivity IP to 90- and 65-Nanometer Process Technologies

Synopsys today announced that it has teamed with UMC to port the Synopsys DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor intellectual property (IP) to UMC's 90-nanometer (nm) and 65-nm technologies

• The TPL Group Paves Way for More Efficient Trial in Texas Court
• CAD benchmarks may improve MP3/MPEG decoders
• Comtech AHA Announces GZIP Compression and Decompression IC
• LSI Announces Strategic Restructuring to Align Resources With Opportunities and Reduce Operating Expenses
• Breakthrough platform from Freescale advances multi-core for embedded markets

Headlines for Wednesday Jun. 27, 2007

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PLDA Breakthrough Demonstration of PCIe Gen 2 in Working Silicon Achieves Industry's Highest Throughput

During the demo, the PCIe link was established at 5 GHz and some of the industry’s best known companies were able to see measured simultaneous throughput of 350 MB/s (write to the server memory) and 380 MB/s (read to server memory)

• Lattice Announces Extensive IP Portfolio For New 90Nm Flash LatticeXP2 FPGA Family
• Altera Ships Production-Qualified Arria GX FPGAs
• Hantro's Multi-Format hardware Video Codecs to Drive Next Generation of Freescale Cellular Handset Solutions
• Qimonda Further Extends Foundry Agreement with Winbond

Headlines for Tuesday Jun. 26, 2007

Top Story

Faraday Launches Silicon-Proven DDR2 Memory Physical Interface IP

Faraday's DDR2 PHY IP, a reliable, cost-effective, and easy-to-integrate memory interface solution, enables semiconductor companies, in a timely manner, to make high performance DDR2 memory interface System-on-Chips (SoCs) for their consumer, automotive, industrial and medical applications

• Mentor Graphics Delivers Verification Solutions for ARM-based Wireless and Multimedia Applications
• National Taiwan University and Altera Corporation Establish EDA/SOPC Joint Laboratory
• Anglo-French IP Partnership announces major design win for its DVB-S2 Modem Technology
• Denali's Verification Software for Flash Memory Systems Leveraged by SST for Mobile and Wireless Applications
• Gaisler Research announces new licensing agreements with leading North American companies
• Kilopass Adds Jeannie Duncanson as CFO
• Xilinx Delivers Spartan-3AN Starter Kit for Rapid Evaluation of Consumer, Communication Infrastructure and Industrial Applications
• OpenCores Web Site to be Sold to a Strategic Partner
• Xilinx Now Shipping Spartan-3A DSP Devices in Production
• AKA Introduces New High Performance 32 bit ARM9-based Smart Logic Module
• GDA Technologies Announces Availability of AdvancedMC Reference Platform for Freescale's MPC8641D Dual Core PowerPC(TM) Processor

Headlines for Monday Jun. 25, 2007

Top Story

Lattice and PLD Applications Announce Partnership For PCI Express Connectivity Solutions

PLDA Delivers PCI XpressLite Core for LatticeECP2M FPGAs; Partnership Focused on Expansion of Connectivity Solutions for Lattice Devices

• Atmel Extends CAP Family of Customizable Microcontrollers With ARM7-based Product
• IMEC offers source code for scalable video coding standard
• Highland Communications Technologies Licenses 2.5 Gbps GPON FEC core to Applied Optoelectronics
• Imagination Technologies and UBC Media Group co-operate to deliver instant music purchase solution
• Beyond Semiconductor Announces New Licensing Agreement with e3C Inc.
• Xilinx Delivers ISE 9.2i With Lower Memory Requirements and New Operating System Support
• Semiconductor Event Highlights Growing Popularity of Logic Nonvolatile Memory in New Chip Designs
• Mobilygen Announces the Industry's Broadest Range of H.264 HD Codec ICs
• FSA Reports Fabless Revenue Totaled $11.7B in the First Quarter Of 2007
• Altera Ships Highest-Density Member of the Cyclone III Family
• Actel Launches Low-Power RTAX-SL FPGAs for Space Applications
• Lattice Introduces Industry's First SERDES FPGA Priced Below $10

Headlines for Friday Jun. 22, 2007

• ARM RealView Microcontroller Kit Supports New STMicroelectronics STM32 Families
• MemCore Announces MemCore-ner, Your Only Web Location for Memory Interface Solutions Information

Headlines for Thursday Jun. 21, 2007

Top Story

STMicroelectronics and Freescale Accelerate Joint Automotive Design Activity

Freescale Semiconductor and STMicroelectronics have made significant progress in the areas of automotive IP development, flash technology alignment and new product definition

• picoChip closes growth round funding of $27 million
• SiRF Technology to Acquire Centrality Communications to Strengthen its Multifunction Location Platform Strategy
• Jetstream and HiTech Global Sign Distributorship Agreement
• ARC Introduces New Modeling and Simulation Products To Speed ''Time to Market'' of ARC-Based SoCs
• ARC International Appoints Steven Gunders As Non Executive Director

Headlines for Wednesday Jun. 20, 2007

• Xilinx Announces Immediate Availability of TD-SCDMA Digital Front-End Reference Design
• MOSAID Licenses Patent Portfolio to Taiwan's Etron Technology
• ARM Announces RealView Compilation Tools for BREW version 3.0
• RadioFrame Networks License CEVA-X DSP Core and Subsystem to Power Femtocell 2G/3G Wireless Base Stations
• VaST Develops High Performance Virtual Processor Model for Freescale’s e200z6 'Power ArchitectureTM' Core
• Tensilica Enhances Reference Flow With Cadence Encounter RTL Compiler
• High Degree of Flexibility Drives Interest in SiP Technology and Increases Demand for SiP Solutions
• Broadcast International Licenses Vanguard Software Solutions Codec

Headlines for Tuesday Jun. 19, 2007

Top Story

Arteris Completes $8.1M Series B Investment Round

Synopsys Leads Investment Along with Existing Venture Firms: Crescendo, TVM Capital and Ventech. Synopsys' investment was driven by the desire of both companies to lower the cost and risk of designing complex system-on-a-chip (SoC) integrated circuits and to foster industry-wide IP reuse capability. The Arteris NoC supports a wide array of IP protocols including ARM® AMBA® 3 AXI(TM), ARM AMBA 2 AHB(TM) and OCP(TM) protocols, which can be used concurrently without modification.

• Xilinx Announces Scalable LogiCORE FlexRay controller IP
• TrendChip Technologies Licenses MIPS32 24KE and MIPS32 34K Cores for Cutting-Edge Broadband Access Solutions
• Rambus XDR Memory Architecture Adopted in Texas Instruments DLP Projector System
• IP Cores, Inc. Announces three low-latency Fast Fourier Transform IP cores for SoC applications in the OFDM-based communications (WiMAX, MBOA, IEEE 802.11) and GPS fields
• Aftek Becomes Tensilica Configurable Processor Authorized Design Center
• MIPS casts doubts on ARM expansion strategy
• Synopsys Announces Virtual Platform for Marvell's PXA3xx Application Processors
• Freescale and Virtutech connect to simplify multi-core Development
• Renesas Technology Releases ''WMA Pro LBR Decode Middleware'' SH-Mobile Software Supporting Windows Media Audio 10 Professional M0 Profile

Headlines for Monday Jun. 18, 2007

Top Story

Chipidea Marks 10th Year Anniversary By Announcing World's First Analog Intellectual Property (IP) Foundry(TM)

Recognizing the semiconductor industry's need for an open market approach to providing comprehensive analog intellectual property (IP) solutions, Chipidea®, the world leader in analog/mixed-signal subsystems and IP, today announced it has created the first Analog IP Foundry(TM) to help customers circumvent the challenges of analog and mixed-signal design.

• NEC Chooses Altera Stratix II GX FPGAs for New ExpEther Interface Technology
• Lattice Semiconductor Announces uLTRON RTOS Support for LatticeMico32 Microprocessor
• ARM9-based Flagship STR910 Microcontrollers from STMicroelectronics now with Higher Performance and Lower Cost
• Actel's Innovative SmartDesign Functionality Eases System-Level Design
• Kilopass and Data I/O Corporation Join Forces to Deliver High-Quality, Affordable SoC Programming Solutions for Mass Production
• Texas Court Ruling Confirms Strength of Moore Microprocessor Patent(TM) Portfolio
• XMOS revealed as configurable fabric company
• Fujitsu Develops Technology for Low-Power, High-Performance 45nm Logic Chips
• Synopsys Acquires ArchPro Design Automation
• Jennic announces ZigBee starter kit for under $200

Headlines for Friday Jun. 15, 2007

Top Story

ARC Acquires Tenison to Speed Time to Market of Customers' Complex SoC Designs; Establishes Cambridge Engineering Center

New Products will Model and Simulate ARC Customers' Chips that Integrate ARC with Non-ARC Intellectual Property

• Aware Extends VDSL2 Interoperability Leadership at NXTcomm 2007

Headlines for Thursday Jun. 14, 2007

Top Story

Jetstream Algorithms become NIST Certified and are now FIPS 140-2 Ready

Jetstream Media Technologies announced today that the algorithms of its security IP cores have successfully passed the Cryptographic Algorithm Validation Program (CAVP), a strict governmental testing program for the validation of semiconductor algorithms

• Cambridge Consultants becomes the first authorised design centre for picoChip's multi-core digital signal processor (DSP)
• The Electronic System Level (ESL) Tools Market: Virtual System Prototyping/Simulation Tools Predicted to Grow Fastest
• DesignArt Networks Picks Tensilica Xtensa LX2 Configurable Processors for WiMAX Baseband Chip
• SiP Technology Attracts Interest as a Potential Alternative to SoC Technology
• MOSAID Signs Two Seasoned Executives as Intellectual Property Licensing Consultants
• The TPL Group Adds ''Legislation'' Forum to Website to Review Sweeping Changes Proposed by the Patent Reform Act of 2007
• New CEO guides Bluespec's changing strategy

Headlines for Wednesday Jun. 13, 2007

Top Story

STMicroelectronics Unveils Design Platform for Low-Power Next-Generation 45nm CMOS

ST confirms early availability of design platform for power-optimized System-on-Chip solutions, including 45nm libraries and first tape-out of 45nm SoC demonstrator IC

• Dust Networks Integrates Kilopass Memory in New Family of Wireless Sensor Networking Products

Headlines for Tuesday Jun. 12, 2007

Top Story

IP Cores, Inc. Delivers a 10 Gbps AES-GCM FPGA Implementation

IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.

• Chartered, Tezzaron Team up to Deliver Ultra High-Speed Memory Solution
• Charlie Hauck Assumes CEO Role at Bluespec
• Renesas Technology Develops Promising Technology for Implementing On-Chip SOI SRAM of 32-Nanometer Generation and Beyond
• iamba Networks and K-micro Team to Develop Market-Leading GPON SoCs

Headlines for Monday Jun. 11, 2007

Top Story

Sidense Qualifies 1T-Fuse(TM) in UMC's 130nm Process

By qualifying the NVM IP, a valuable memory addition to the foundry's IP Alliance Program, UMC's customers now have access to a low-cost, highly secure embedded NVM for applications such as electrical fuse replacement, flash and mask-programmable ROM replacement, code storage, RFID, unique ID, encryption, key storage, HDMI, and digital rights management (DRM).

• DAC panelists call for IP reuse standards
• STMicroelectronics Reshapes the MCU Market with New 32-Bit Family Powered by ARM Cortex-M3 Core
• Industry Ships 25 Million XDR DRAM Memory Devices
• Alma Technologies launches its new generation JPEG 2000 Encoder Core
• Mentor Graphics Acquires Sierra Design Automation; Answers Industry Need for Design-to-Fab Flow for 65 and 45 Nanometers
• Automotive standard open to interpretation

Headlines for Friday Jun. 08, 2007

Top Story

IP business model 'broken,' says exec

The IP business is ''broken'' and needs consolidation to better serve customers, according to Mike Kaskowitz, vice president of semiconductor IP at Mosaid Technologies Inc.

• MOSAID Announces Changes to Board of Directors
• TSMC May 2007 Sales Report
• Virage Logic Strengthens Executive Management Team with Two Key Appointments
• Xilinx Provides June Quarter Guidance

Headlines for Thursday Jun. 07, 2007

Top Story

Aware Announces Licensing Agreement with PMC-Sierra for VDSL2

StratiPHY3 intellectual property supports ADSL, ADSL2 and ADSL2+ as well as VDSL1 and VDSL2 and allows silicon providers to combine a complete, field-proven DSL solution with the strength and diversity of their own silicon product offerings to penetrate the world's largest broadband access market.

• Faraday Monthly Sales Report -- May 2007
• Forte Announces Cynthesizer 3.3 with First SystemC to GDSII Flow; Adds SystemC Behavioral IP Library and Graphical Analysis Environment
• Xilinx Cuts Development Time for Hand-Held Devices with New Low-Cost CoolRunner-II Starter Kit
• Comsys baseband processor is first WiMAX multi-technology
• Tri-Vision signs Microtek to V-chip licenses

Headlines for Wednesday Jun. 06, 2007

Top Story

EE Times - DAC special: Video interview with Synopsys CEO Aart De Geus

Aart de Geus, chairman and CEO of Synopsys Inc. (Mountain View, Calif.), looks a decade ahead to discern the future direction of the EDA industry in an interview at this week's Design Automation Conference.

• Analysis: Synplicity's 'Hardi' ASIC prototyping play
• Two Korean Universities License Tensilica's Xtensa Configurable Processor
• Luminary Micro Launches 27 Stellaris Microcontrollers Including the First Offering of Real- Time Networking with the ARM Cortex-M3 Processor

Headlines for Tuesday Jun. 05, 2007

Top Story

EE Times - DAC special: video interview with Sidense CEO Xerxes Wania

Xerxes Wania, president and CEO of logic IP developer Sidense Corp. (Ottawa), spoke with EE Times editor-in-chief Brian Fuller at the Design Automation Conference.

• Sarnoff Europe and UMC Sign IP Alliance for ESD Protection
• Synopsys Launches VMM Catalyst Program With More Than 50 Member Companies
• Sonics Plus Partners Equals Complete ESL Strategy
• Patriot Scientific Names Jim Turley as President and CEO
• EDA Leaders Team With MIPS Technologies to Support New High-performance MIPS32(R) 74K(TM) Core Family
• VSIA Quality IP Metric Now Includes Verification IP Extension
• Digital Blocks Extends the DB9000 TFT LCD Controller IP Core Family with the availability of the DB9000AHB for the AMBA 2.0 Interconnect
• CoWare, AXE, and BeatCraft Integrate CoWare Virtual Platform, axLinux and JAKAR Media Framework
• Kolorific Licenses MIPS32 24KEc Core for Next-Generation iDTV Applications

Headlines for Monday Jun. 04, 2007

Top Story

ARM Unleashes Adaptive Verification IP For On-Chip Communication

Adaptive Verification IP combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually. Adaptive Verification IP complements existing random or directed-random methods with a powerful new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in SoC size and complexity to continue.

• Dust Networks chooses DOLPHIN Integration's unique Low Leakage memory to extend the performance of its Wireless Sensor Networking Products
• CAST JPEG 2000 Encoder Core now Faster and More Capable
• Sunplus Selects SonicsLX(TM) for Portable Media Player SoC
• Lattice Delivers Industry's Fastest Memory and HyperTransport Technology I/O
• UMC and ARM Partner to Deliver Comprehensive SOI Solutions for 65nm Technology
• CAST Offers PCI Express Model, Highlights APS 32-bit Processor Cores at DAC 2007
• TSMC Announces Active Accuracy Assurance Initiative
• TSMC Unveils Reference Flow 8.0 to Address 45nm Design Challenges
• videantis and Pro Design realize real-time H.264/AVC encoding on CHIPit Platinum system
• FS2 Introduces System Navigator Probe for Development using the New Ultra Low Power Handshake Solutions Memory Extension HT80C51 Core
• ProDesign Introduces the CHIPit Platinum V5 and Reaches a New Level in High-End ASIC and SoC Prototyping
• IBM, Chartered and Samsung Extend Integrated DFM Support for Common Platform Technology to 45nm

Headlines for Friday Jun. 01, 2007

Top Story

Chipidea's New USB PHY Architecture for 1.8V Devices Offers Industry's Lowest Power Consumption for SoC Designers

Chipidea, the world's leading provider of analog/mixed-signal subsystems and intellectual property (IP), today introduced a new generation USB physical layer architecture using 1.8V IO devices that offers the industry's lowest power consumption for System-on-Chip (SoC) designs in the 65nm and 45nm advanced technology nodes.

• Lightspeed Logic collaborates with Cadence to deliver Reconfigurable Logic Reference Flow
• MunEDA's tool family, WiCkeD, is selected by Faraday for its Analog IP Porting
• Synplicity Announces Agreement to Acquire HARDI Electronics AB