D&R Headline News (December 2007)

Headlines for Monday Dec. 31, 2007

• TSMC Announces Multi-layer Mask Service

Headlines for Thursday Dec. 27, 2007

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Commentary: A few fabless fables

The semiconductor industry is commoditizing with opportunities to differentiate being few and far between. As the fabless companies jostle and compete for market positioning and market share, they are subject to the larger trends that transact in the fabless supply-chain world.

Headlines for Wednesday Dec. 26, 2007

• SMIC and IBM Sign Licensing Agreement

Headlines for Monday Dec. 24, 2007

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Unicorn Investment Bank acquires 75% equity stake in Open-Silicon

Unicorn announces the investment of US$190 million to acquire a 75% equity stake in Open-Silicon. Unicorn is partnering with Open-Silicon’s senior management team to fulfill the company’s next phase of growth, which includes global expansion.

• Shift in the integration equation
• Under the Hood: Silicon TV tuners clearing hurdles

Headlines for Friday Dec. 21, 2007

Top Story

Sidense Broadens OTP Offering with Additional Process Nodes at SMIC

Sidense today announced that its one-time programmable (OTP) technology is available on Semiconductor Manufacturing International Corporation’s (SMIC) 180nm and 90nm processes.

• Mentor Graphics Announces Interoperability of Serial ATA Intellectual Property Solution
• MPEG LA Sues Audiovox for Breach of MPEG-2 and 1394 Patent Pool Contractual Obligations
• CEVA, Inc. to Divest Equity in GloNav, Inc. Following GloNav's Acquisition By NXP Semiconductors for $110 Million
• Verigy Purchases Moore Microprocessor Patent Portfolio License
• Transmeta Appoints Dan Hillman as Vice President of Engineering

Headlines for Thursday Dec. 20, 2007

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Infineon Broadens Availability of Embedded Flash Process

Infineon today announced an agreement with IBM to broaden the availability of Infineon's proven, high-volume Embedded Flash process. Infineon's 130nm Embedded Flash technology will be licensed to IBM and will be available for new chip designs manufactured by IBM in North America.

• Digital Blocks Announces the DB-I2C Controller IP Core with the availability of Master-Slave, Master, and Slave Versions for the AMBA 2.0 APB Interconnect
• Winbond Electronics Signs New License to MOSAID Patent Portfolio
• Product Announcement: ARM RealView Logic Tile for the Xilinx Virtex-5 XC5VLX330 FPGA
• Global Leader in Digital Entertainment Solutions Licenses Power-efficient MIPS32 24KEc Pro Core
• Fabless, Analog IC Provider Silicon Line Secures Funding to Pursue Fast-Growing Markets for Its Patented PHY Layer Chips

Headlines for Wednesday Dec. 19, 2007

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Altera Shipping Full Line of 65-nm Cyclone III FPGAs

Altera today announced that all eight members of its low-power, low-cost Cyclone® III family of 65-nm FPGAs are now shipping in production quantities.

• Rambus Revises Fourth Quarter Revenue Guidance
• SANYO Leverages Altera Cyclone II FPGAs to Bring High-End Vehicle Camera Features to Broad Market

Headlines for Tuesday Dec. 18, 2007

Top Story

Wipro-NewLogics WiLD 801.11a/b/g IP Reference Platform receives Wi-Fi Certification

Wipro-NewLogic is announcing that its WiLD IP VD4 reference platform has been Wi-Fi CERTIFIED for IEEE802.11a, IEEE802.11b, IEEE802.11g, WPA - Personal, WPA2 - Personal, WMM, IEEE 802.11d and IEEE 802.11h.

• ChipX Slashes Cost of System-on-Chip Development With Hybrid ASIC
• Chips&Media Now Supports RealVideo HD in Hardware IP
• TPL, Toshiba, Matsushita (Panasonic), and JVC Resolve Their Dispute Over the Moore Microprocessor Patent Portfolio
• TPL and NEC Electronics America Resolve Their Dispute Over the Moore Microprocessor Patent Portfolio
• Tensilica Adds Dolby Digital Consumer Encoder and Dolby Digital Compatible Output 5.1-Channel Encoders to Xtensa HiFi 2 Audio Engine Codec Library

Headlines for Monday Dec. 17, 2007

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ChipX and Recognetics Partner to Deliver Pattern Recognition ASIC for Security, Data Mining and Imaging Applications

ChipX today announced the successful implementation of a complex, 10 million gate design for pattern recognition using Recognetics' neural network technology.

• MIPS Technologies Announces CFO to Step Down in February
• Toshiba Licenses Rambus XDR Memory Architecture for HDTV Chipset
• NEC Electronics America Integrates Analog Copy Protection From Dwight Cavendish Systems Into EMMA-Based MPEG Decoder Devices
• Averant and AerieLogic to Ease the Usage of Formal Property Verification
• Actel Delivers Battery-Powered Icicle Kit Based on Industry's Lowest Power FPGA
• ARC Appoints Bill Jackson as Vice President of Marketing
• Ian Barton Joins Silistix as Managing Director of Silistix UK
• Lattice Announces Production Release of Entire 90nm LatticeECP2M FPGA Family
• 1394 Trade Association Announces 3.2 Gigabit per Second Speed for FireWire

Headlines for Thursday Dec. 13, 2007

Top Story

ARC configures a design flow for system-on-chip

Configurable cores and subsystems developer ARC International (St. Albans, England) has developed and is refining a systems development platform that it says will change the way mobile multimedia systems are being designed.

• TSMC Unveils New 65-Nanometer Mixed-Signal and RF Tool Qualification Program
• Stratix III FPGAs Achieve 533-MHz DDR3 Interface Performance
• ON Semiconductor to Acquire AMIS Holdings in an All-Stock Transaction Valued at Approximately $915 Million
• Leading Industry Analyst Firm Names Nios II Processor as FPGA Industry's Number One Soft Processor Core

Headlines for Wednesday Dec. 12, 2007

Top Story

Arasan Chip Systems Completes UNH Interoperability Testing for 10/100 Ethernet Solutions Suite

The Arasan 10/100 Ethernet Solution provides all the components needed for development, from the IP core to the Verification IP, software drivers and the hardware development platform. The IP core includes RMM compliant synthesizable RTL for 10/100 Media Access Controller (MAC) Core with MII or optional RMII interface, easy-to-use test environment and synthesis scripts.

• STMicroelectronics Samples 65nm Hard Disk Drive Iterative Decoding Channel
• Lattice Delivers Industry's Fastest QDR II/II+ Memory Controller Support
• MIPS Technologies Announces CFO to Step Down in February
• Wind River Enhances On-Chip Debugging Solutions to Address Growing Complexities in Mobile and Handheld Device Development

Headlines for Tuesday Dec. 11, 2007

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Sun Accelerates Growth of UltraSPARC CMT Eco System; Releases OpenSPARC(TM) T2 Processor RTL to Open Source Community

Sun Microsystems Inc. today delivered on the commitment it made in August by providing the OpenSPARC(TM) T2 RTL (register transfer level) processor design to the free and open source community via the GPL license. The OpenSPARC T2 processor is based on the UltraSPARC(R) T2 processor, the world's fastest commodity processor with eight cores and eight threads per core running the Solaris(TM) 10 Operating System (OS).

• STMicroelectronics to Acquire Genesis Microchip
• Mobius Microsystems Raises $10.22 Million in Series B Financing
• Entropic Licenses MIPS32 24Kc Core for Next-Generation Broadband and Residential Gateway Applications
• Micronas USA Licenses DRM Solution from Elliptic
• Wireless semiconductor veteran Johan Lodenius joins Coresonic board
• TSMC Reports Foundry's First 32-Nanometer Technology with Functional SRAM
• UMC Releases 65nm DFM Design Enablement Kit
• Alpine Electronics Purchases Microprocessor Patent Portfolio License

Headlines for Monday Dec. 10, 2007

Top Story

Effort behind reusing IP blocks is underestimated

When intellectual property (IP) reuse entered the IC design paradigm more than ten years ago, the semiconductor industry expressed high expectations. IP reuse was indeed seen as a way to foster development productivity and output that would eventually offset the design productivity gap.

• Compute intensive apps to drive innovation in IP technology
• AMD, Intel at it again, as both take aim at SoC
• Tensilica Enhances Xtensa Configurable Processor Families with New Options, Bridges and Software Tools
• Virage Logic Partners with MTEK I&C to Bring Its Advanced Silicon Aware Intellectual Property (IP) to the Korean Design Community
• UMC's 90nm URAM Used in Mobile TV Applications
• Arrow Electronics and Triad Semiconductor Team to Offer Mixed-Signal Via-Configurable Array ASICs
• ARM Announces Processor Licensing Agreement With PMC-Sierra For Cortex and MultiCore Processors
• Chipidea Introduces Industry's First Class D Audio Driver IP for Portable Consumer Applications
• TSMC November 2007 Sales Report
• Altera Zeros Out Power With New MAX IIZ CPLDs for Portable Applications
• OneSpin Solutions Delivers First Equivalence Checker Dedicated to FPGA Synthesis Verification
• Leica Geosystems selects Wipro-NewLogic to provide turnkey IC design & supply chain management services
• Tensilica Offers Integrated Real-Time Trace Support to Xtensa Configurable and Diamond Standard Processor Cores
• STMicroelectronics Migrates Chips to Advanced 45nm CMOS RF TechnologySTMicroelectronics Migrates Chips to Advanced 45nm CMOS RF Technology
• Xilinx Powered SGI RC100 Reconfigurable Computing Platform Accelerates Bioinformatics Application Over 900X
• IBM Alliances Deliver Easier Path to Next Generation Semiconductor Products
• Virage Logic and Marketech International Corporation (MIC) Partner to Provide Silicon Aware Intellectual Property (IP) to Rapidly Growing China, Singapore, and Taiwan Markets
• Actel Drives Industry's Lowest Power FPGAs into Portable Displays

Headlines for Friday Dec. 07, 2007

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IP business model to continue to exist, says analyst

Semiconductor intellectual property (IP) as a real market emerged about ten years ago, and although detractors said there was no money to be made in IP, this sector has outgrown both the EDA and semiconductor markets.

• Faraday Monthly Sales Report -- November 2007
• Nuvation opens Electronics Design Center in Shanghai, China
• WMS Gaming Joins List of Patriot's Microprocessor Licensees
• Lite-On Purchases Microprocessor Patent Portfolio License
• Moortec Announce route2IP - a Collaborative Initiative for Sub-Picosecond Jitter PLL Design
• Cadence Joins the HyperTransport Consortium

Headlines for Thursday Dec. 06, 2007

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New Intel group will drive system-chip design

Intel has created a new system-on-chip enablement group under Gadi Singer, a veteran executive who has led many high profile projects for the company. The move comes at a time when the company is accelerating efforts both in multicore PC processors as well as a range of SoCs for sockets outside its traditional PC markets.

• ARC readies energy saving cores
• TI Delivers First Single-Chip, Real-Time HD Video Transcoding Solution with DaVinci(TM) Technology

Headlines for Wednesday Dec. 05, 2007

Top Story

Cadence and ARM Deliver Reference Methodologies for Multicore and Low-Power Devices

Cadence Design Systems, Inc. and ARM today announced the availability of two new implementation reference methodologies jointly developed by the companies, one for the ARM11™ MPCore™ multicore processor and the other for low-power implementation of the ARM1176JZF-S™ processor, which incorporates ARM® Intelligent Energy Manager (IEM™) technology

• Microtronix Enhances 1080p Display Quality With Altera Cyclone III FPGA-Based Development Kit

Headlines for Tuesday Dec. 04, 2007

Top Story

Palmchip announces AcurX-Lite SoC Platform for Wireless Mobility

AcurX-Lite readily interfaces with major CPUs and proven 3rd party IP cores for the Wireless Mobility market. The new AcurX-Lite, comes with CPU bridge, memory subsystem bridge, DMA controller bridge, power management, interrupt controller, watchdog,general-purpose timers, two UARTs, I2C, SPI master, and a real-time clock. It supports multiple CPU cores (ARM, MIPS, ARC, Tensilica), multiple memory subsystems, 3rd party (Mentor, Synopsys) PCI, USB, Ethernet, Wireless and Video IP on a single chip.

• Vector Informatik Adopts Altera Cyclone III FPGAs for Network Interface Product Line
• Chipidea Achieves Certification for USB High-Speed PHY IP on Chartered’s 90nm and 65nm Customer-ready Technologies
• Daewoo Electronics Purchases Moore Microprocessor Patent Portfolio License
• ARM and Esterel to Deliver Software Development Tools for Safety-Critical Systems
• Xilinx Delivers Complete Virtex-5 FPGA Based Solutions for SPI-4.2 and SFI-4.1 Interfaces
• Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling

Headlines for Monday Dec. 03, 2007

Top Story

Motorola Taps IPextreme to Bring Advanced Semiconductor Technology to Market

IPextreme, Inc. today announced that the company is bringing advanced Motorola clock generation technology to market in the form of licensable semiconductor intellectual property (IP)

• Sidense OTP Integrated in XMOS Programmable Semiconductor
• Lattice Partners with Oregano Systems to Introduce IEEE 1588 Industrial Ethernet IP Core
• CORTUS, DOLPHIN Integration and RAISONANCE form a partnership for the cores of price-sensitive high-performance SoC
• DxO Labs Announces Immediate Availability of DxO IPE, the Industry's First Embedded Image Processing Solution (ISP) for Camera Phones with Built-in Enhanced Depth of Field (EDOF) and Optical Fault Correction
• Express Logic Introduces ThreadX RTOS Support for Tensilica's New Diamond Standard 106Micro
• XMOS unveils first Software Defined Silicon
• TSMC Ships One-Millionth 12-Inch 90NM Wafer Fast ramping process reaches milestone in 4½ years
• UMC Foundry Design Kit for New Cadence Virtuoso Platform Speeds Production of 65nm Designs
• Cadence Boosts Engineers' Productivity with Advances in Enterprise Verification Offering