D&R Headline News (April 2008)

Headlines for Wednesday Apr. 30, 2008

Top Story

videantis introduces new scalable video solutions up to HD for mobile devices

By combining powerful video engines with a programmable stream unit, the v-MP20x0MOB solution packages are capable of encoding and decoding video up to 720p resolution in a wide range of standards on extremely small silicon area without placing load on the host CPU.

• Virage Logic Reports Second Quarter Fiscal Year 2008 Results
• GiDEL Releases the Fastest, Scalable SoC/ASIC Verification System Built on Largest and Fastest FPGA's
• Imagination Technologies Signs Licence Agreement with Samsung Electronics
• Mobile Handset Industry Leaders Form a Working Group to Drive New Memory Interface Standard
• MoSys, Inc. Reports First Quarter 2008 Financial Results
• Appeals Court Sides with Rambus in Samsung Matter

Headlines for Tuesday Apr. 29, 2008

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TranSwitch announces first HDMI 1.3 PHY IP Core operating at 10.5 Gbps

The HD-PXL-1.3 transmitter IP core is available in two versions. The first version meets all the current HD (High Definition) standards up to 2.25 Gbps. The second version supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps.

• Arasan Chip Systems Announces PCI Express Gen2 End Point Solution
• Tensilica Adds Dolby TrueHD Decoder to Xtensa HiFi 2 Audio Engine Codec Library
• ARM Holdings plc Reports Results For The First Quarter Ended 31 March 2008
• CEVA, Inc. Announces Record First Quarter 2008 Financial Results
• ASPEED Technology Purchases IP from IPextreme Core Store
• Altera and HCELL Engineering Announce DO-254-Certifiable Nios II Embedded Processor
• Maxim Integrated Products and Altera Offer a Simple, Cost-Effective Solution to Protect FPGA Designs

Headlines for Monday Apr. 28, 2008

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Synopsys Releases Silicon Proven 5.0 Gbps PCI Express 2.0 PHY IP

The DesignWare PHY IP for PCI Express 2.0 includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options, providing both ease of integration into a SoC, and ensuring high production yields.

• ASIC Architect Announces the Availability of DDR 3 Controller Cores
• ASIC Architect Announces the Availability of Multi-Port Intelligent Arbiter and Scheduler for DDR Controller Cores
• MOSAID Grants First Wireless Patent Portfolio License to Matsushita Electric
• CSR Selects Virage Logic as Its Trusted IP Partner for Next-Generation Bluetooth Devices
• ARM and Mindspeed Address Next Generation Home Gateways with Multiprocessing Technology
• Multiple Configurable ARC Cores Enable ITT to Build Secure Communications Devices for Government Applications
• Lattice Announces New CPLD Family For Low Power, High Volume Portable Applications
• TSMC wants more of IC pie
• Onkyo Purchases Moore Microprocessor Patent Portfolio License
• MIPS Technologies Launches Company's First European University Program for Design Engineers
• Dolphin Integration announces a SESAME Library stem for ultra low power and low voltage in 0.18 um

Headlines for Friday Apr. 25, 2008

• Rambus Reports First Quarter Results

Headlines for Thursday Apr. 24, 2008

Top Story

ARC Introduces New "Sonic Focus-Ready" Audio/Video Subsystem

The AM 401V offers a fully integrated yet programmable subsystem that is capable of playing back virtually any audio/video content on portable media devices. An industry first, it is optimized to popular audio formats such as AAC, MP3, Dolby Digital and video standards such as MPEG-4, Real Video, VC-1 and H.264 while greatly improving sound fidelity.

• First Batch of China 3G Commercial Trial Handsets are all ARM Powered
• SMIC and Amlogic in Commercial Production of 90nm Digital Photo Frame Chip
• Faraday Reported 2008 First Quarter Results
• DoD may push back on Apple's P.A. Semi bid; PowerPC variant designed into many military systems

Headlines for Wednesday Apr. 23, 2008

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Rambus Announces IBM to License Multi-protocol Serdes

This multi-protocol SerDes cell provides IBM with a high-performance and low-power solution for implementation on its 45nm silicon-on-insulator (SOI) technology.

• Rambus Signs Memorandum of Understanding with Spansion
• Apple enters IC market, buys PA Semi
• DC Circuit Court Overturns Federal Trade Commission Orders in Rambus Case
• Synplicity Announces First Quarter 2008 Results
• Silicon Image Reports First Quarter 2008 Financial Results

Headlines for Tuesday Apr. 22, 2008

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Virage Logic's DDR Memory Controller Interface Provides High Performance Data Transfer at Higher Efficiency and Lower Power

Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth.

• Actel Partners With Pigeon Point Systems to Deliver TCA Management Solutions
• TSMC Unveils New 40/65-Nanometer SPICE Tool Qualification Program
• Kilopass Non-Volatile Memory Technology Embedded in 15 Million Units
• ChipVision Delivers Two Breakthrough ESL Power-Optimization Design Tools for Meeting Critical Power Budgets
• ChipX Mixed-Signal ASIC Processes and Procedures Satisfy DO-254 Standard
• Winbond Electronics Corporation and Qimonda AG Announce New Agreement for 65 nanometer Buried Wordline Technology Transfer
• RIM and The TPL Group Agree to Moore Microprocessor Patent(TM) Portfolio License
• MPEG-2 Patent Owners Sue Target Corporation for MPEG-2 Patent Infringement

Headlines for Monday Apr. 21, 2008

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Northwest Logic Announces Availability Of A Complete PCI Express 2.0 Solution For Xilinx Virtex-5FXT Devices

This solution combines Northwest Logic’s full-featured PCI Express 2.0 Core, DMA Back-End Core, DMA Driver and PCI Express GUI to provide a complete, pre-packaged PCI Express 2.0 solution.

• Impinj Introduces Few-Time Programmable Logic Nonvolatile Memory Solution
• CEVA Unveils High-Performance, Low Power Platforms for Wireless, Multimedia Applications
• SMIC and ASTRI Collaborate on the Development of the World's First Dual Mode UWB MAC ASIC Supporting Both WiMedia Compliant WLP and China IGRS Networking Applications
• Lattice and Aldec Announce New Alliance For FPGA Design And Verification
• Actel Corporation Licenses Sarnoff's TakeCharge Solution
• Evatronix SDIO-HOST Controller compliments the company's line of memory controllers
• Lattice Semiconductor and Synplicity Extend Partnership
• Renesas collaborates with IMEC on reconfigurable RF transceivers
• Executive Interview: Xilinx chairman Wim Roelandts

Headlines for Friday Apr. 18, 2008

• Virage Logic Appoints Dr. Alex Shubat to Newly Created Position of Chief Operating Officer
• Legend Silicon Releases 3rd Generation DTV Demodulator Chip

Headlines for Thursday Apr. 17, 2008

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Kilopass Announces XPM Is First CMOS Logic NVM Technology to Complete Qualification on 80nm and 90nm Process Technologies

Kilopass Technology today announced that its extra-permanent memory (XPM) technology is the first high density embedded NVM technology to complete qualification for 80nm and 90nm process technologies with the successful qualification of its XPM-80GC and XPM-90LP product families.

• Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
• eASIC Shatters FPGA Performance With 235MHz LEON3 Processor
• Digital Core Design announces D6802 8-bit Microprocessor Core
• Altera Announces First Quarter Results; Increases Quarterly Dividend
• National Instruments LabVIEW Targets Industry-Leading ARM Microcontrollers

Headlines for Wednesday Apr. 16, 2008

Top Story

Arasan Chip Systems Introduces New Low Voltage SDIO Validation Platform

The new SD/SDIO Device HVP is a SD host platform tool based upon Arasan's SD/SDIO host controller used for SDIO device validation. Fully compliant with SD/SDIO v2.0, SD Memory v2.0, and MMC v4.3, the SD socket can interface to any standard SD or MMC card for fast validation.

• Start-up OptNgn Offers a Floating Point VHDL Library as Open Source
• Keynote speakers differ on the health of the US patent system
• Sun and Wind River Partner to Deliver Carrier Grade Linux for Next-Generation Networking on Sun's UltraSPARC(R) T2 Processor
• SoC cost, complexity driving IP collaboration
• Accelerating development and lowering risk
• China moves to bolster IP laws

Headlines for Tuesday Apr. 15, 2008

Top Story

Silicon Image Delivers Advanced 12 Megapixel Camera Processor IP Core for Mobile Devices

This technology delivers professional picture quality and advanced camera functionality once only found in digital still cameras (DSCs), but now conveniently integrated into mobile phones, portable multimedia players (PMPs), ultra mobile PCs (UMPCs) and security cameras.

• GDA Announces the Availability of PCI Express Single Root IOV (GPEX-SRIOV) IP
• Synopsys Delivers Industry's First Certified USB 2.0 PHY IP for Advanced 45-Nanometer Process
• On2 Licenses Mobile Optimized Decoders to Monsoon Multimedia
• Synplicity Launches ReadyIP Program: The Industry's First Universal, Secure IP Flow for FPGA Implementation
• MediaTek Licenses CEVA-X DSP Core and Subsystem from CEVA
• MIPS Technologies Introduces Industry's First Hot Spot Analyzer for Fast Linux Kernel Profiling
• Synplicity Introduces System Designer: System-Level Implementation and IP Integration Tool for FPGA Design
• RC Module announces new SD/HD H.264 Decoder SoC aimed at Russian DVB market
• Zensys Picks Kilopass XPM Memory for Wireless Remote Control Applications, The Next Generation of Home Control and Automation
• LatticeECP2M FPGAs Support High-Speed Serial JESD204 Specification
• Dolphin Integration announces an embedded high rejection LDO powering sensitive Analog Components
• TSMC Announces Power Trim Service for Advanced Chip Leakage Power Reduction
• ARM Joins Synplicity's ReadyIP Program
• Tensilica Joins Synplicity’s ReadyIP Program and Offers Free Production- Ready Processor Core for FPGAs

Headlines for Monday Apr. 14, 2008

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ARM Enhances Feature Set of Popular Cortex-M3 Processor for Extreme Low-Power Functionality

The latest release includes a new Wake-Up Interrupt (WIC) controller which allows almost instantaneous return to fully active mode from an Ultra-Low Leakage (ULL) retention state and introduces enhanced power management features that address the ongoing need in the embedded market for increased performance and longer battery life in next-generation designs.

• CoWare Introduces First Ever Checkpoint / Restart Capability for Native SystemC Virtual Platforms
• Gennum Delivers Low Power, PCI Express 2.0, Infiniband Repeater for System Interconnects
• Xilinx Unveils Embedded Development Environment and Ecosystem Supporting New Virtex-5 FXT FPGAs
• QuickLogic and Sital announce development Partnership for MIL-STD-1553 core
• Global Unichip Announces First Full Service SiP Production Flow in the Fabless ASIC Industry
• AMCC and Redpine Signals Collaborate on Next Generation Power Architecture-Based Embedded Wi-Fi Connectivity Solutions
• ARM and Express Logic Enhance Out-of-Box Experience for ThreadX Development with RealView Tools
• Energy Micro Licenses Cortex-M3 Processor
• MIPS Technologies to Showcase Digital Entertainment, Networking and Microcontroller Innovations at ESC 2008
• Xilinx Demonstrates New Triple-Rate SDI Reference Designs for Broadcast Video Applications at NAB 2008
• Xilinx Virtex-5 FPGA Powers New Universal Multi-Channel Processor From Miranda Technologies
• Xilinx and OmniTek Successfully Deploy Advanced Video Processing Platform
• Xilinx Virtex-5 FPGA Accelerates Development of Ross Video Multi-Definition Keyer for Digital Broadcast Production Applications

Headlines for Friday Apr. 11, 2008

Top Story

Gaisler Research Announces Nucleus OS Support for The LEON Processor

Gaisler Research today announced that Mentor Graphics Nucleus® Operating System (OS) is now supported on the LEON3 processor.

• Kodak Selects intoPIX Technology for Digital Cinema
• STMicroelectronics Achieves Highest Memory Density for ARM9 Standard MCUs, Delivering Pin- and Function Compatibility with Embedded Flash of 288 Kbytes to 2.1 Mbytes
• Analysis: Is the ST, NXP wireless JV the start of IDM break-up?
• STMicroelectronics and NXP Merge Wireless Businesses to Expand Product Breadth and Boost Innovation
• eASIC Appoints ASIC and FPGA Industry Expert Mo Movahed as Vice President of Software Engineering
• Commsonic Showcases Cyclone3 Modulators at NAB 2008
• ClioSoft Introduces Enterprise Edition of the SOS Design Data Collaboration Platform

Headlines for Thursday Apr. 10, 2008

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PLDA announces immediate availability of PCIe 2.0 IP Core supporting new Xilinx Virtex-5 FXT FPGAs

PLDA, the industry leader in the high-speed bus IP market, today announced the immediate availability of their PCIe Gen 2 FPGA IP support for the Virtex®- 5 FXT platform.

• Strength of the ARM Ecosystem Demonstrated at ESC with More Than 50 Partners Showing ARM Technology
• TSMC March 2008 Sales Report
• Patriot Scientific Reports Q3 FY'08 Results
• Motion Computing Licenses Wi-LAN Wireless Technologies

Headlines for Wednesday Apr. 09, 2008

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Barco announces a complete set of HD and DCI JPEG 2000 encoder and decoder video boards

Barco Silex is pleased to announce its new DCPB-2000 family of JPEG 2000 PCI-Express Acceleration boards. Capitalizing on its leadership in real-time and high-definition JPEG 2000 IP cores, this family of boards encodes and decodes JPEG 2000 in real-time.

• GSA Reports 2007 Semiconductor Industry Revenue Totaled $267.5 B
• Sarnoff Releases New H.264/AVC Bitstreams for OpenCable
• Analog design alive and growing in India
• Imaging Solutions Group (ISG) announces High Speed FireWire(tm) IEEE-1394b Intellectual Property
• Ocean Blue develops software for High Definition interactive TV
• COCONUT Project to Define a Modeling and Verification Flow for Embedded Platform Design
• Kevin Kennedy to Step Down From Rambus Board of Directors
• HDMI Licensing Appoints Steve Venuti as New LLC President; HDMI Adoption Continues to Grow

Headlines for Tuesday Apr. 08, 2008

Top Story

Alchip Licenses ARM CPU, Fabric IP and Physical IP to Provide SoC Solutions

Alchip Technologies, Inc. and ARM today announced that Alchip has licensed the ARM926EJ-S(TM) processor, Fabric IP and ARM® Physical IP to advance system-on-chip (SoC) design solutions to its customers worldwide

• Altera Demonstrates 3-Gbps SDI Leadership and 1080p Video Framework at NAB Show 2008
• Harris Corporation Selects Altera Stratix II GX FPGAs for Platinum Line of Routing Switchers
• Imagination Technologies Licenses Third POWERVR SGX Graphics Core to Renesas
• Xilinx Appoints Semiconductor Industry Veteran Victor Peng Senior Vice President of New Silicon Engineering Group
• New X-FAB 0.18 Micrometer Process Maximizes Cost-Effectiveness in Analog/Mixed-Signal Chip Design for Commercial Automotive and Power Management Applications

Headlines for Monday Apr. 07, 2008

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Wipro-NewLogic demonstrates IEEE 1394b Link IP Cores for PC, Consumer, Storage & Automotive applications

In one of the demonstrations for 1394b OHCI Link, Wipro showcased data transfer between an external Hard Disk Drive and a PC along with simultaneous streaming of video from the external hard disk. The PC was connected to Wipro’s PCI based platform running the IEEE 1394b OHCI IP core along with Window’s IEEE 1394 drivers and a 3rd party PHY.

• NXP and CoWare Establish Strategic Relationship for the Company Wide Deployment of ESL Technologies
• Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process
• Dolphin Integration announces an ultra High Density library in shrunk processes.
• Xilinx Introduces the Industry's Highest Performance, Largest Capacity FPGAs for Space Applications
• Faraday Monthly Sales Report -- March 2008
• Altera Broadens Markets for Arria GX Family
• Gennum Delivers Industry's First Single-Chip HD and 3Gb/s Transmit and Receive Solutions

Headlines for Friday Apr. 04, 2008

• Wi-LAN Files Motion to Dismiss Marvell Complaint

Headlines for Thursday Apr. 03, 2008

Top Story

Novelics Announces Availability of Single-Transistor SRAM for 65-nanometer System-On-Chip Desgin

coolSRAM-1T™Is Only 65nm SRAM-1T Available in Standard Bulk CMOS process for High-Density Embedded Memory Applications

• Impinj's AEON/MTP Multiple-time Programmable Nonvolatile Memory Licensed by Avago Technologies
• Ambric and MainConcept Collaborate to Accelerate High Definition Video Compression
• EDA Consortium Reports 6.7 Percent Industry Revenue Growth in Fourth Quarter 2007

Headlines for Wednesday Apr. 02, 2008

Top Story

Synopsys' New DesignWare IP Significantly Simplifies Transition to PCI Express

The DesignWare LE IP for PCIe is a cost-effective solution that provides ease-of- use features to simplify the complexities of transitioning to PCI Express for applications requiring a single lane, such as existing PCI/PCI-X designs, ExpressCards, Ethernet controllers, SATA controllers and wireless hubs.

• Commentary: How to cash in on video IP
• NXP Semiconductors and IPextreme Launch Ground-breaking Methodology for Semiconductor IP Design
• GCT Semiconductor Announces the Industry's First Single-Chip Solution Supporting Both Mobile WiMAX IEEE 802.16e Wave 2 and WiFi 802.11 b/g
• Chartered Extends Technology Development Collaboration with IBM to 22-Nanometer Process Node
• Hynix and Grandis Sign License and Joint Development Agreement on Spin-Transfer Torque MRAM
• Imagination Technologies confirms new Intel Centrino Atom processor technology utilises POWERVR graphics and video technologies
• New MultiBench Multicore Benchmarks Now Available from EEMBC Provides an Extensive Tool to Test Multicore Systems
• intoPIX demonstrates its new 4K JPEG 2000 encoder in the Xilinx booth at NAB 2008
• Vimicro Names MIPS Technologies Key Supplier of Analog/Mixed-signal IP and Subsystems

Headlines for Tuesday Apr. 01, 2008

Top Story

Fujitsu Introduces 65-Nanometer 10G SerDes from Prism Circuits

Fujitsu Microelectronics America today announced a new collaboration with Prism Circuits to develop a single-lane, variable-data-rate SerDes macro. Built using Fujitsu’s 65-nanometer CS200HP process technology, the macro will be available in the third calendar quarter of 2008.

• Magnum Semiconductor Licenses Sidense's Logic Non-Volatile Memory for Consumer Entertainment Products
• MIPS Technologies Unveils Industry's First Multi-threaded, Multiprocessor IP Core for the Embedded Market
• Springsoft and Novas Agree to Merge
• Beceem Introduces World's First Single-Chip, 65 Nanometer Mobile WiMAX Solution - Sets New Standard for Low Power Consumption
• Xilinx Ships Virtex-5 FXT FPGAs, Delivering the Ultimate in System Integration for Designs That Demand High-Performance Processing and High-Speed Serial I/O