D&R Headline News (May 2008)

Headlines for Friday May. 30, 2008

Top Story

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solutions

The new Xilinx 3GPP LTE Turbo Encoder and Decoder LogiCORE(TM) offerings deliver throughput speeds of up to 200 Mbps with the embedded digital signal processing (DSP) capabilities of Spartan(R) and Virtex(R) field programmable gate arrays (FPGAs)

• MOSAID Announces Share Buyback Program
• Synopsys Introduces HAPS-51T ASIC Prototyping System to Accelerate Time to Results
• Lattice Semiconductor Appoints Interim CEO

Headlines for Thursday May. 29, 2008

Top Story

Denali First to Release Full DDR3 DIMM IP Solution

This new DDR3 DIMM offering adds unique capabilities in the memory controller and PHY IP that are needed for networking, storage and personal computing systems using DDR3 modules at data rates up to 12.8GBytes/s per DIMM.

• Tower Semiconductor Implements Cost Reduction Plan
• Gleichmann Research announces a 2-FPGA-Board with free partitioning software
• NemeriX Awarded Patent For Single-Chip Multi-Band GNSS RF Receiver Technology

Headlines for Wednesday May. 28, 2008

Top Story

Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution

Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions.

• Synopsys Releases Proven VMM Methodology Standard Library and Applications Under Apache Open Source License
• Synochip adopts Elliptic's Public Key Cryptography Engine and Ellipsys Software
• DapTechnology announces VHDL Testbench for its FireLink Extended 1394b link layer controller IP Core
• eMemory Cooperate with Fujitsu to Offer 0.18um HV and Logic Embedded NVM Technology
• Faraday Technology and NemoChips Team-Up to Build Next Generation Low Power Mobile Platform based upon the Cadence Low-Power Solution

Headlines for Tuesday May. 27, 2008

Top Story

EVE Unleashes DW-FPGA for FPGA Synthesis

EVE, the leader in hardware/software co-verification, today announced availability of DW-FPGA, a DesignWare® foundation library for use with field programmable gate array (FPGA) synthesis software.

• eASIC Appoints Distinguished ASIC Expert Dr. Ranko Scepanovic as Senior Vice President of Advanced Technology
• Duolog Technologies Provides OCP-IP Members Powerful OCP Transaction Analysis Tool
• LogicVision Introduces Dragonfly Test Platform
• Numetrics Adds New Executive to Team
• OCP-IP Releases OCP 2.2 Revision A
• IPextreme Adds New Representative in China: S2C
• Sonics Bundles JEDA OCP Checker Into SonicsStudio
• SpringSoft Completes Merger with Novas, Acquires More Technology and Channel Companies
• Total solution for standard cell & I/O library, and memory IP characterization by Legend's tools
• STMicroelectronics Strengthens Position in Wireless Segment
• Part 2 of OCP-IP's Network On Chip Benchmarking Specification Released to Member Review
• Synopsys Unveils New IC Compiler Router Delivering 10X Speed-Up

Headlines for Monday May. 26, 2008

• CoFluent Design Announces World's First Eclipse-Based Graphical ESL Modeling and Simulation Framework
• S3's Advanced Set-Top Box Development Endorsed by STMicroelectronics
• NEC Electronics Introduces Cost-Effective EMMA SoCs with Built-In Support for Next-Generation H.264 Video Compression Standard
• STMicroelectronics Introduces First 65nm SPEAr(R) Customizable Chip for Computer Peripherals Applications
• Wi-LAN and ASUSTeK Sign Multi-Year Wi-Fi License Agreement

Headlines for Thursday May. 22, 2008

Top Story

Denali Software Announces Availability of MMAV 2008 Verification IP

This latest package release provides a complete and an accurate solution for simulating memories, including support for most of the memory technologies, including DRAM, SRAM, Flash, and Card memories, and several standard protocols.

• Mentor Graphics Reports Fiscal First Quarter Results
• Industry Collaboration Marches Ahead with Official Release of DDR PHY Interface Specification Version 2.0 Accelerating DDR Memory System Development
• eSilicon Achieves Significant Milestone by Booking Production Orders from More Than Fifty Customers
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2008
• Denali Software to Leverage Bluespec Technology for Next-Generation Memory Controller IP Development
• MathStar, Inc. to Engage Investment Banker

Headlines for Wednesday May. 21, 2008

Top Story

Arteris Announces Completion of $7.5M Series C Investment

DoCoMo Capital Joins Existing Investors, Synopsys, Crescendo, TVM Capital and Ventech to Fund the Leading NoC Interconnect Solution Provider

• Xilinx Adds Flexible Connectivity to Low-Power Intel(R) In-Vehicle Infotainment Reference Design
• IP Square Licenses ColdFire Architecture
• ARM Licenses Latest Multiprocessor Technology to Toshiba
• MSIM Simulator with 5X~10X Speedup for Characterizing CCS Timing Model of Cell Library

Headlines for Tuesday May. 20, 2008

Top Story

MIPS Technologies Unveils Silicon-Proven Hi-Fi Audio Playback IP With Lowest Power Consumption Available

The new Audio Codec IP achieves an impressive 100dB dynamic range and -93dB THD while consuming only 7.8mW power when playing back through stereo line outputs at 48kHz.

• Sidense's Board of Directors Welcomes Two Industry Veterans
• Cissoid Completes Second Round of Investment
• Tower Semiconductor to Acquire Jazz Technologies
• EVE to Showcase Transaction-Level Modeling Capabilities During DAC

Headlines for Monday May. 19, 2008

Top Story

Altera Announces Industry's First 40-nm FPGAs and HardCopy ASICs

The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates.

• Algotronix launches unique DesignTag system for detecting proprietary intellectual property within an operating chip
• Evatronix announces its fifth 8051 ISA-based SoC Development Platform - HDLC Connectivity.
• NEC develops Adobe Flash Lite IP
• Silicon Image Appoints New Vice President of Engineering
• Conexant Launches World's First Family of Speakers-on-a-Chip Semiconductor Solutions
• ASOCS Unveils World's First Wireless MultiComm Processor
• GENUSION to Share Superior Reliability Findings for Award-Winning B4-Flash Memory and Logic NVM IP

Headlines for Friday May. 16, 2008

• Dolphin Integration: The sales turnover of the first semester tarnished by the shadow of the dollar
• ChipVision Closes on $4.5 Million Series B Round

Headlines for Thursday May. 15, 2008

Top Story

Synopsys Adds 30 New Titles to DesignWare System-Level Library

The new members of the Library include high-performance transaction-level models (TLMs) for PowerPC®, MIPS, and DesignWare IP. DesignWare System-Level Library models significantly reduce the time to create virtual platforms and are written in SystemC to work in any IEEE 1666 (SystemC)-compliant simulation environment.

• Mentor Graphics Acquires Assets of Ponte Solutions -- Technology to be Integrated into Calibre DFM Solutions
• Pantel and IPextreme to Develop Reliable 911 Emergency Dispatch for VOIP Phone Users
• Mistral Announces Its First Solution on the ARM Cortex-A8 Processor
• New customers select the LEON3 processor for multimedia applications
• Atmel's 400 MHz ARM9-based Embedded Microprocessor Consumes Only 80 mW in Active Mode

Headlines for Wednesday May. 14, 2008

• Certicom Delivers Digital Content Protection Solution to Micronas
• K-micro and AnSem form a strategic partnership to develop chipsets for the home networking market
• Xilinx Helps Designers Meet High-Speed Connectivity Requirements With High-Performance Configuration and Storage Solution for Virtex-5 FPGAs

Headlines for Tuesday May. 13, 2008

Top Story

Faraday Announces Successful Implementation of 533 MHz ARM(R) Compliant Core -- FA626 in 130nm SoC ASIC

Faraday Technology today announced that it has successfully integrated a hardened 533Mhz ARM(R) compliant core -- FA626 in a complex 130nm SoC ASIC for Radioframe Networks.

• Sidense SLP Memory IP Targets Low Power OTP Applications
• Mindspeed Selects CEVA-X1641 DSP and CEVA-XS1200A Subsystem for High Performance Next Generation Network Applications
• Virage Logic Embedded Multi-Time Programmable Non-Volatile Memory Gains Acceptance in Military Applications
• HiSilicon Selects Synopsys as IP Vendor Of Choice for SoC Designs
• OCP-IP Releases Survey of Network on Chip Architectures
• UMC and Mentor Graphics Introduce Foundry Design Kits (FDK) for Mixed-Mode and RF Technologies
• Cosmic Circuits Announces New IP-cores with "Ready for IBM Technology" Validations
• PrKERNELv4 from eSOL Supports Faraday's ARMv4 ISA-based FA526 Processor
• Tokyo Electron Device Announces New Imaging Application Evaluation Platform Equipped With Spartan-3 Generation FPGA

Headlines for Monday May. 12, 2008

Top Story

TranSwitch announces Industry’s Most Flexible Programmable Silicon Platform for Access Applications

The first platform, Taurus, which is targeted for access applications, provides programmability, flexibility and cost effectiveness unsurpassed in the market. Taurus includes a targeted set of access interfaces, including GPON, Ethernet, and POTS/TDM.

• Court Of Appeals Summarily Affirms ARM Litigation Victory Over TPL and Patriot
• Zilog's broader 32-bit MCU move: Too little, too late?
• ARM Announces PrimeCell Generic Interrupt Controller
• Government agency BICRO supports Xylon project with $1 Million
• High-performance MIPS32 24K Processor Core Powers New GPON Residential Gateway SoC from BroadLight
• Dolphin Integration: A Commercial Breakthrough for 'Reduced Cell Stem Libraries'
• VeriSilicon Joins Power Forward Initiative to Accelerate Advanced Low-Power Design
• Xilinx Introduces the World's Highest Performance Reconfigurable DSP Solution
• Synopsys Donates Proven VMM Methodology Library and Applications to Accellera
• Actel Introduces IGLOO-Based Portable Control Solutions
• CoWare and Agility Team to Accelerate the Simulation of Complex DSP Algorithms
• Peking University Press to Publish a Chinese Edition of the Arm-Synopsys 'Low Power Methodology Manual'

Headlines for Friday May. 09, 2008

• Bruce Dunlevie Appointed Chairman of Rambus Board of Directors
• TSMC April 2008 Sales Report
• Cosmic Circuits joins Cadence Openchoice Program

Headlines for Thursday May. 08, 2008

Top Story

ARM Extends Its Long-Term Investment In India With A Dedicated VLSI Test Lab

The new VLSI test lab will provide analysis of VLSI libraries and ARM® physical IP to correlate design to silicon behavior. This activity has increasingly become a Partner requirement prior to SoC tapeout as technologies have increased in complexity and mask costs have escalated.

• Transmeta Reports First Quarter 2008 Results
• Hynix - ProMOS Sign Amendment to Strengthen Long-term Strategic Alliance
• New Customer Win in High Growth Flash Market Highlights ARC's Growing Leadership
• TM Technology Adopts ARC for Multimedia Storage Solutions
• Zilog Partners With ARM for New 32-Bit Microcontroller Solutions
• NextIO Standardizes on VMM Methodology and Synopsys VCS for Next-Generation I/O Virtualization Chip
• Virtutech Simics Selected by General Dynamics for U.S. Navy MUOS Project

Headlines for Wednesday May. 07, 2008

Top Story

Did Apple invest in P.A. Semi prior to acquisition?

Word on the street is that there is still a little more light to be shed on the saga of P.A. Semi and Apple.

• Cypress Unveils Online Solutions Library of IP To Facilitate Faster, More Efficient PSoC Designs
• Faraday Monthly Sales Report - April 2008
• Comtech AHA Reaches the 20 Year Mark in Offering Forward Error Correction Hardware
• ASIC specialist eSilicon expands strategy, seeks acquisitions
• Strategy Analytics: ARM Will Beat Intel in $17 Billion Mobile Internet Device Market
• TranSwitch Corporation Announces First Quarter 2008 Financial Results
• IPextreme Named "Cool Vendor" in Semiconductors by Leading Analyst Firm

Headlines for Tuesday May. 06, 2008

Top Story

Allegro introduces world's first H.264/MPEG-4 AVC High-Profile/High-Definition Hardware Video Encoding IP

Allegro’s H.264 IP core is a real-time hardware encoder targeting mobile phones, camcorders, set-top boxes, webcams and video surveillance applications. Allegro’s IP core can process images up to high-definition resolutions.

• Virage Logic Announces Stock Repurchase Program
• Virage Logic's High-Efficiency DDR Memory Controller Selected by Server Virtualization Solutions Leader 3Leaf Systems
• EVE Ends Fiscal Year 2008 with 40% Growth in Revenues
• ARM Enables Rapid Deployment of Microsoft Windows Embedded CE on ARM Processors with RealView ICE
• Intel, Samsung Electronics and TSMC Reach Agreement for 450mm Wafer Manufacturing Transition
• Synopsys Invests In Prover Technology
• Expanded VPX DSP offering with two more products based on the Freescale MPC8641D and Xilinx Virtex-5 FPGAs
• KABEN selected as "One of Canada's Hottest 20 Innovative Companies"

Headlines for Monday May. 05, 2008

Top Story

ARM job-cutting moves on to tools group

Having embarked on a restructuring of its physical intellectual property division (PIPD), processor licensor ARM Holdings plc (Cambridge, England) is now moving on to restructure its development systems business, according to Warren East, CEO and president.

• Altera's Stratix III FPGAs Support SGMII on LVDS I/Os
• GSA contends fabless is more
• Lawrence Berkeley National Laboratory and Tensilica Collaborate on Design of Energy-Efficient Supercomputing for Climate Research
• New Release Of Lattice FPGA Design Tools Extends Performance And Productivity
• Iveia Announces the Titan-V5e Small Form Factor Processing Module Utilizing System-On-A-Chip Technology and the Xilinx Virtex- 5 FXT
• Big changes seen in foundry rankings
• The new challenge for tech companies: currency fluctuations

Headlines for Friday May. 02, 2008

Top Story

NXP mulls IP licensing for its Mifare platform

NXP Semiconductors is looking seriously at licensing to other semiconductor companies its Mifare contactless chip card platform technology for use in SIM cards and NFC applications such as ticketing, payment and access management.

• Cadence Delivers Silicon-Ready Reference Methodologies for ARM Cortex-A9 Processor

Headlines for Thursday May. 01, 2008

Top Story

MIPS Technologies Reports Third Quarter Fiscal 2008 Financial Results

Revenue for the third quarter was $27.3 million, an increase of 3 percent over the prior quarter revenue of $26.5 million and an increase of 43 percent from the $19.1 million reported in the third fiscal quarter a year ago. Q3 revenue growth was driven primarily by increased license fees.

• ARM Joins Unified Extensible Firmware Interface Forum
• MOSAID Sells Selected Patents to SAtech Group A.B. Limited Liability Company