D&R Headline News (June 2009)

Headlines for Tuesday Jun. 30, 2009

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eInfochips Announces VMM-Enabled MIPI CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys DesignWare Verification IP Alliance Program

eInfochips today announced the availability of Verification Methodology Manual (VMM)-enabled MIPI® CSI-2 (Camera Serial Interface), DSI (Display Serial Interface), HSI (High Speed Synchronous Interface) & SDIO Verification IP (VIP)

• ARC International: Trading Update and Outcome of Strategic Review
• SMIC Achieves Silicon Success with High Performance 45-nanometer Process
• Virage Logic Sees Strong Adoption of Company's Broad 40nm IP Product Portfolio
• FFT Library from OptNgn Validated for use in Mentor Graphics' Precision FPGA Synthesis
• Dolphin Integration's Audio converter Helium lightens both Power consumption and Bill-of-Material
• The SPIRIT Consortium Approves IP-XACT Version 1.5

Headlines for Monday Jun. 29, 2009

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Samsung using 45-nm process for ARM-11 based processor

Samsung Electronics Ltd has started sampling its ARM11-based application processor that will be made on its 45-nm CMOS process technology.

• Sarnoff Europe Completes Management Buy-Out of Sarnoff's ESD Protection Business
• Altera Announces New Cyclone III LS FPGAs
• SMIC Revises Up Second Quarter 2009 Quarter-on-Quarter Revenue Guidance
• Chinese Academy of Sciences Selects Vivante as GPU Partner for Netbooks
• TSMC Enhances 0.13um Family
• New Package Option for Lattice MachXO PLD Family Reduces Cost and Board Area
• Virage Logic Joins Power.org Community; Provides Power Architecture Customers Extensive Range of Silicon-Proven Semiconductor IP

Headlines for Friday Jun. 26, 2009

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Tiempo, IP company with breakthrough ultra-low power asynchronous design technology, raises 5 million Euros ($7 million) in Series B funding

Tiempo today announced it has closed a 5 million Euros Series B financing round with two new investors, Viveris Management and Oddo Private Equity. Previous Series A investors, i.e. EmerTec Gestion, Schneider Electric Ventures, INPG Entreprise SA and Alma Capital Finances, also participated to this round.

• Imagination Technologies Group plc - Preliminary Results for the twelve months to 30 April 2009
• Imagination Technologies Group plc - Listing of Shares
• Licensable IP houses leapfrogging DSP incumbents
• MOSAID Reports Results for Fourth Quarter and Year-End Fiscal 2009 and Dividend

Headlines for Thursday Jun. 25, 2009

• MIPS32 Processor Powers Innovative DTV Platform from NXP
• MindTree Partners with Bluetooth Special Interest Group to Develop MCAP Test Suite for PTS

Headlines for Wednesday Jun. 24, 2009

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Xilinx Accelerates Development of Next-Generation Systems With Industry's First Deployment of Targeted Design Platforms

Xilinx today released the Xilinx Base Targeted Design Platform aimed at accelerating the development of system-on-chip (SoC) solutions with Xilinx(R) Virtex(R)-6 and Spartan(R)-6 field programmable gate arrays (FPGAs).

• XMOS puts multi-core in mass market for under US$ 5 per core
• HHTech. launched a new generation Cortex-A8 emulator
• Memory interface IP sector heats up
• Wind River Extends JTAG Development Tools for Freescale, Intel and RMI Processors
• Samsung Electronics and Numonyx join forces on Phase Change Memory
• Cadence and Xilinx Simplify SoC Development With Enterprise Verification Capabilities for FPGA Targeted Design Platforms
• GLOBALFOUNDRIES Announces New Fab 2 Executive Leadership Team
• Rambus Announces the Pricing of Its $150 Million Convertible Senior Notes Offering

Headlines for Tuesday Jun. 23, 2009

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Silicon startups get the squeeze

Top venture capitalists say opportunities are changing and narrowing for semiconductor startups because the costs of bringing a new processor or system-on-chip to market are becoming prohibitive and raising new funds to invest in high tech companies of any kind is getting increasingly difficult.

• Rambus Demonstrates Superior Power Efficiency of World's Fastest Memory
• Sonics Combines DRAM Scheduler with Synopsys Protocol Controller For Integrated High-Performance Memory Subsystem
• Virage Logic's AEON(R) Becomes the First Multi-Time Programmable Embedded Non-Volatile Memory Available on a Standard CMOS Process Qualified to Rigorous Automotive Standard AEC-Q100
• Industry's Fastest Growing Standard for DDR-PHY Interface Specification Expands With LP-DDR2 and DDR3 Support
• Rambus Updates Second Quarter Guidance
• Synopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs
• SMIC and Synopsys Announce the Availability of Reference Flow 4.0
• UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for its 65nm and 40nm IC Reference Flows

Headlines for Monday Jun. 22, 2009

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Tensilica Announces High-Performance ConnX Baseband Engine for LTE and 4G Wireless DSP Handsets and Base Stations

Tensilica today announced the first member of its new ConnX family of digital signal processor (DSP) cores for system-on-chip (SOC) design. The ConnX Baseband Engine enables efficient baseband processing for 3G, LTE (Long-Term Evolution) and 4G wireless equipment with its scalable, high-performance DSP architecture that provides industry leading computational throughput of 16 18-bit MACs per cycle.

• Dolphin Integration puts in the public domain a unique freeware for evaluation of Standard Cell libraries
• Perfectus Announces Industry's First SystemVerilog-based OVM Tested ONFi Verification IP for ONFi 2.1 Specification
• Silicon Image Introduces First Products Incorporating HDMI 1.4 Features for DTV and Home Theatre Applications
• ARM Provides Technology For LG Electronics Digital TVs
• BitSim launches ARM based Qt platform
• Tensilica Announces Strategic Investment by DOCOMO Capital
• Imagination Technologies licenses high-performance graphics processor core to MediaTek
• SpringSoft and TSMC Commence Joint Development of Multi-Node Process Design Kit Portfolio
• The Open Patent Alliance Issues Call for WiMAX Patents
• Calypto Delivers Industry's First Automated Tool for Memory Power Optimization

Headlines for Friday Jun. 19, 2009

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VinChip Announces India's First Homegrown 32-Bit RISC Processor

VinChip Systems announces the immediate availability of its convergent 32-bit RISC processor, VinRZ5110. Its DSP enhanced instruction set architecture, low power design and optimized gate count makes it well suited for DSP and other embedded applications.

• Intel increases stake in graphics cores provider Imagination
• CoWare and EVE Link Electronic System Virtualization and Emulation for ARM AXI-based Systems
• Tiempo Demonstrates the First Asynchronous Synthesis Tool Using Standard Languages
• SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1

Headlines for Thursday Jun. 18, 2009

• EASIC CEO resigns, Vasishta regains title
• Tower Semiconductor to Manufacture Next-Generation MRAM from Crocus Technology
• NEC Electronics and Toshiba Extend Chip Technology Development Agreements with IBM
• Ittiam Systems announces new audio software bundle for Texas Instruments' C64x+ Digital Signal Processors
• RedMere Support For HDMI 1.4 Specification

Headlines for Wednesday Jun. 17, 2009

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Movidia Licenses Arasan's SD/SDIO IP Core for Next-Generation Multi-Media SoC

Arasan announced that Movidia, a fabless semiconductor company based in Dublin, Ireland, specializing in video editing technology for mobile phones, has licensed Arasan's Secure Digital SD/SDIO/MMC Host IP and SD/SDIO Combo Device IP for its next generation SoC.

• TSMC Reports Foundry's First 28 Nanometer Low Power Platform Technology with Fully Functional 64Mb SRAM
• CebaTech Hires Joe Rash as Vice President of Business Development and Marketing
• Synopsys and Actel Renew OEM Relationship for FPGA Design Software
• TES Signs Licence Deal for Ultra-wideband Wireless Technology

Headlines for Tuesday Jun. 16, 2009

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Innovative Logic announces fully integrated USB3.0 Controller with PCS layer

Innovative Logic announced today the second release of USB 3.0 Device Controller IP. Inno-Logic’s USB3.0 IP offering includes implementation IP as well as verification IP by making use of industry standard latest tools and methodologies.

• Silistix Extends Its Industry Leading Asynchronous CHAIN(R)works Product Family With the Introduction of CHAINworks Sync
• Elliptic Announces Name Change and Strategy Update - Becomes Elliptic Technologies Inc.
• Socle Adopts Platform Core Compiler to Accelerate Customer SoC Design
• eASIC and IPextreme Announce Freescale ColdFire Processors for Nextreme NEW ASICs
• ARM Mali GPUs Achieve Industry-Firsts With Khronos OpenGL ES 2.0 Conformance For 1080p and Multicore
• Soitec's 300mm Ultra-Thin SOI Ready to Support Mainstream Ramp Up of Fully Depleted Applications at 22nm Node
• Paradigm Works Distributes ReleaseWorks As Free, Open Source Software

Headlines for Monday Jun. 15, 2009

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CoWare Reduces Design Cost for Complex ARM AMBA Platform Optimization

CoWare announced the availability of a new Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect, enabling early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM® AMBA®-based virtual platforms.

• BroadLogic Paves the Way to a New Era in Narrowcast and Unicast Cable Services with the Industry's First Ultra-Dense QAM Modulator Chip
• SiliconBlue Launches "Turbo" Speed Version of Ultra-Low Power iCE65 mobileFPGA Family
• Arteris and Duolog Streamline SOC Integration Design Flow
• China's Institute of Computing Technology Licenses Industry-Standard MIPS Architectures
• UMC Announces Retirement of Mr. Tony Yu as President of UMC-USA Office
• STMicroelectronics Unveils Ultra-Low-Power Technology Platform for 8-bit and 32-bit Microcontrollers, Enabling Next-Generation Power-Saving Products
• Imagination Technologies to include Sorenson Spark video decoder on its video cores to enable playback of the widest selection of internet video
• Agnisys announces free download of a smart IP Documentation tool
• Lattice Announces Updates and Enhancements to its FPGA Design Tool Suite
• Synopsys Continues Galaxy Custom Designer Momentum with 2009.06 Release
• Geo Semiconductor Inc. Launches Operations

Headlines for Friday Jun. 12, 2009

• Sun starts porting OpenSolaris to ARM chips
• Chartered Updates Guidance for Second Quarter
• Noesis Technologies Releases Fully Configurable Interleaver-Deinterleaver IP
• Rambus Reaches Tentative Settlement with European Commission
• Actel Corporation Reduces Second Quarter Guidance

Headlines for Thursday Jun. 11, 2009

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Cadence Announces Restructuring

Upon completion, Cadence expects to achieve annual operating expense savings of approximately $30 million, through a combination of workforce and other expense reductions.

• Altera CFO to Resign
• EDA Standards Organizations Accellera and The SPIRIT Consortium Announce Plans to Merge
• ARM Utliizes eASIC Devices to Validate Cortex-A9 MPCore Multicore Processor-Based Devices
• Foundry rankings change as shortages near
• Sonics Joins IPextreme's Constellations Program

Headlines for Wednesday Jun. 10, 2009

Top Story

TSMC May 2009 Sales Report

TSMC today announced its net sales for May 2009: on an unconsolidated basis, sales were approximately NT$24.47 billion, an increase of 12.6 percent over April 2009 and a decrease of 15.6 percent from May 2008.

• Atmel Upgrades SAM9261S to Higher-frequency SAM9G10 ARM9-based Embedded Microprocessor
• Avalon Announces the Issue of their First US Patent
• Jazz Semiconductor Achieves ISO/TS 16949 Automotive Quality Management System Certification
• Melfas Chooses ARM Cortex-M0 Processor For Capacitive Touch Screen Controllers
• X-FAB Releases First 0.18 Micrometer Foundry Solution for Integrated Hall Sensors
• XDR DRAM Surpasses 100 Million Units Shipped

Headlines for Tuesday Jun. 09, 2009

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Silicon Clocks Completes $10.3M Series C Financing Led By Silicon Labs and Premier Venture Firms

Silicon Clocks, a leader in integrated timing solutions for electronic systems, today announced the completion of a $10.3M Series C financing to enable the company to ramp into full production the J-Series family of low jitter timing products, as well as transition its cutting edge CMEMSTM (Standard CMOS + MEMS) process technology into commercial products.

• Sidense OTP Memory IP Enables SpectraLinear Non-Volatile Programmable PC Clock Family
• Arasan expands Analog capability through Acquisition
• Algotronix provides AES encryption over USB with new reference designs
• PixArt Takes ARC License as a Platform For Image Processing Solutions
• TranSwitch Integrates Tensilica Xtensa Processors into its Atlanta 2000 Gigabit-rate Communications Processor
• GDA Technologies, Inc. Joins Power.org Community Strengthening the Power Architecture Roadmap and Enabling Power Architecture Solutions in Growth Market Areas
• Sital's 1553 IP is used by NASA
• TSMC Selects Synopsys Galaxy Implementation Platform for Integrated Sign-off Flow
• TSMC Selects Legend's Model Diagnoser for Standard Cell Library Quality Assurance

Headlines for Monday Jun. 08, 2009

Top Story

Gennum's Snowbush IP Group Delivers the Industry's First PCI Expess 3.0 PHY IP on TSMC 40nm Process

Gennum today announced that its Snowbush IP group has developed the industry’s first available integrated PCI Express® 3.0 (Gen 3) PHY and Controller IP solution. The new PCIe® 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies, enabling early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8.0 Gigatransfers per second (GT/s) performance of this new PCI-SIG standard. PCIe 3.0 opens up more bandwidth using the same physical connectors and adds new features to improve the user experience in server network and computer products using PCI Express.

• Rambus Moves To Withdraw Patents From ITC Proceedings Against NVIDIA
• PLX Technology Selects Snowbush IP PCI Express 3.0 PHY for Next-generation Switches
• Vivante Corporation Signs 15th GPU Licensee
• CEO Interview: Cadence's Tan plans to build on analog strength
• Analysis: CEVA's reversal of fortune
• Ember Unveils Industry's Highest Performance ZigBee Chips
• Synopsys Enables System Design Interoperability With System-Level Catalyst Program
• MoSys Acquires Prism Circuits, Inc.
• IHP selects SMASH for natural mixed signal design
• Casio Selects Cadence C-to-Silicon Compiler for High-Level Synthesis
• Lattice Announces New Automotive Qualified Chip Scale 132 BGA Packaging for the LatticeXP2 Family

Headlines for Friday Jun. 05, 2009

Top Story

Analysis: Intel eyes embedded apps with Wind River deal

There will undoubtedly be fallout from Intel Corp.'s move into the embedded software market, a market well beyond its traditional PC and server segments.

• DeFacTo Demonstrates to TESSOLVE the Effectiveness of its RTL Testability Sign-off Solution
• X-FAB Announces Quarterly Results
• Wi-LAN Litigation Update
• Faraday Monthly Sales Report -- May 2009
• HelloSoft Announces WiMAX/WiFi Handset Based on Its HS100 IP Convergence Processor

Headlines for Thursday Jun. 04, 2009

Top Story

Intel to Acquire Wind River Systems for Approximately $884 Million

Intel Corporation has entered into a definitive agreement to acquire Wind River Systems Inc, under which Intel will acquire all outstanding Wind River common stock for $11.50 per share in cash, or approximately $884 million in the aggregate.

• CAST Expands Video IP Cores Line with New Video Deinterlacer
• Fujitsu Microelectronics Solutions Adopts EVE's ZeBu Emulation Platform to Develop Embedded Software Before Tapeout
• RF Engines Ltd wins new contract with EONIC of the Netherlands
• Wi-LAN Reports Second Quarter 2009 Financial Results and Declares Dividend
• Synopsys CEO: Crisis will change the way chips are designed
• Dolphin Integration launches the design of a SoC as an Archipelago for leakage control with the PERK cell Library

Headlines for Wednesday Jun. 03, 2009

Top Story

Synopsys Announces First DDR3 IP Verified in Silicon at 1600 Megabits per Second

Synopsys today announced that its DesignWare® DDR3/2 PHY and digital controller IP is the first DDR3 IP that has been fully verified in test silicon at 1600 Megabits per second (Mbps), the maximum data-rate of the JEDEC DDR3 specification.

• Altera Eases Development of 40-nm FPGAs with Stratix IV GX FPGA Development Kit
• Developers of control, automation and instrumentation applications can jumpstart designs with TI's new cost-efficient ARM Cortex-M3-based Stellaris MCU kits
• ARC Launches New Sound-to-Silicon Solution Aimed at the High-Growth Media Phone Market
• New ARC Sound-to-Silicon Solution Targets Revitalized Mobile Digital TV Market

Headlines for Tuesday Jun. 02, 2009

Top Story

Palmchip Stimulates Economic Recovery by Offering Free Semiconductor IP Cores

Palmchip today announced the launch of their “SoCStart” IP Program providing free semiconductor IP cores. The company is also announcing the AcurX-51™, a SoC platform with integrated 8051 core. Designers can use this SoC platform to quickly start their SoC chip project. AcurX-51 is ported into Xilinx FPGA for rapid firmware and software development.

• Cavium Networks Introduces Industry Leading Integrated ECONA ARM Processor for Small Form Factor Applications
• U.S. Patent and Trademark Office Rejects Patent Claims That Rambus is Asserting Against NVIDIA
• Arasan Chip Systems appoints New Sales Director
• eInfochips announces DDR2 SDRAM SystemVerilog & VMM based Memory Model Generator Tool
• SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development
• SMIC and CHINGIS Announce Availability of 0.18um Embedded Flash Process Technology and IP Portfolio
• Sequans Introduces Second Chip in New Generation 65nm Mobile WiMAX Chip Family
• Qualcomm Introduces Single-Chip 802.11n Wireless LAN Solution for Handsets and Mobile Devices
• Innovasic Semiconductor Announces the Availability of Pin-Compatible 80C186XL and 80C188XL Embedded Processors
• Altera Updates Second Quarter Guidance

Headlines for Monday Jun. 01, 2009

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Altera Ships Highest Density, Highest System-Bandwidth FPGA Targeting 40G/100G Applications

Altera today announced availability of the industry's highest density, highest system-bandwidth FPGA to address the stringent demands of today's bandwidth-heavy applications. Featuring 11.3-Gbps transceivers and 530K logic elements (LEs), the Stratix® IV GT EP4S40G5 and EP4S100G5 FPGAs are the latest variants of Altera's 40-nm Stratix IV FPGA family shipping to customers.

• Atmel Introduces Industry's First ARM Cortex-M3 Flash MCU With On-Chip High Speed USB Device-and-Transceiver
• MIPS Technologies Announces Availability of Android Platform on MIPS Architecture
• Socle Partners with Catena, CoreSonic to Drive Wireless SoC Platform in 65nm as Mobile Solution
• CYIT Selects Vivante to Meet the GPU Needs of TD-SCDMA Wireless Devices
• EEMBC Opens New CoreMark Embedded Processor Benchmark to the Industry
• Xilinx and LynuxWorks Demonstrate Avionics Application Solution
• Silicon Image Launches SteelVine(R) Series 3 Core Storage Processor and SATA Port Multiplier
• ARM Announces Support For EEMBC CoreMark Benchmark
• C80186EC IP Core Added to the Evatronix 80186 Replacements Family
• ARC's Sonic Focus Audio Technology Now Available on ViXS XCode 3290 SoC to Enable a Rich Audio/Video Consumer Experience
• NetLogic Microsystems Announces Definitive Agreement to Merge with RMI Corporation