D&R Headline News (July 2009)

Headlines for Friday Jul. 31, 2009

• Agilent and Wi-LAN Enter Wireless License Agreement
• HDL Design House announces Serial Rapid IO soft IP core (HIP 3300)
• Imagination Technologies considers growth by acquisition

Headlines for Thursday Jul. 30, 2009

Top Story

Mentor Graphics Unveils Android and Embedded Linux Strategy with Acquisition of Embedded Alley

By combining Embedded Alley’s Android and Linux products and services with the Mentor Graphics Nucleus® real-time operating system (RTOS), tools and middleware, Mentor can now provide device manufacturers with all the software they need to build their products, and work closely with them throughout their product lifecycle to supply tools and services at every stage.

• Possible offer for ARC International PLC
• TSMC Reports Second Quarter EPS of NT$0.94
• Mentor Graphics Announces Nucleus Graphics and Linux Platform for ARM Mali GPUs

Headlines for Wednesday Jul. 29, 2009

Top Story

Arasan Chip Systems First to Announce e.MMC 4.4 Card Controller IP Core

Arasan announced the availability of the Embedded MultiMedia 4.4 Card Controller IP compliant with the recently ratified JEDEC e·MMC 4.4 standard. Arasan’s e·MMC 4.4 Card Controller enables memory card designers to support the higher bandwidth and new security, card partition features offered by e·MMC 4.4.

• Cadence Reports Q2 2009 Financial Results
• Virage Logic Reports Third Quarter Fiscal 2009 Results
• picoChip and Elliptic Collaborate on Comprehensive Security Solution for Femtocell SoC
• Altera Extends Temperature Range of Stratix III FPGAs to Support Military Applications
• CEVA, Inc. Announces Second Quarter 2009 Financial Results
• GLOBALFOUNDRIES Announces Strategic Customer Engagement with STMicroelectronics
• TSMC keynoter touts cooperative business models
• ARM Sees Demand For HD Mobile Media And Entertainment Grow As Mali GPU Licensing Momentum Continues
• MOSIS Marks Expanded Semiconductor Foundry Offerings With Shuttle Runs for Silicon-On-Insulator (SOI)
• eMemory's Neobit OTP reaches 1 million wafer production mark; IP solutions for 65 nm processes launched
• MoSys, Inc. Reports Second Quarter 2009 Financial Results
• Actel Announces Second Quarter 2009 Financial Results

Headlines for Tuesday Jul. 28, 2009

Top Story

Virage Logic Introduces Volume Production-Proven SiPro PCI Express PHY IP

Virage Logic today announced its new offering, a silicon and volume production-proven 40-nanometer (nm) G PCI Express Gen1/Gen2 Physical Layer (PHY). The SiPro™ PCI Express PHY product line represents the first offering in Virage Logic’s advanced interface IP SiPro product portfolio that is a result of its collaboration with AMD announced in January 2009.

• Physical layer and protocols provide complete MIPI IP solution for SoC development
• Altera's 40-nm Arria II GX FPGAs Achieve PCI-SIG Compliance for PCIe Express 2.0 Specification
• The TSMC Tsunami at DAC 2009
• Virage Logic Extends IP Technology Leadership to the 32/28nm Process
• Fujitsu Launches USB 3.0 to SATA Bridge IC
• austriamicrosystems to manufacture Triad Semiconductor's Via-Configurable SoC Solution
• ARM Holdings plc Reports Results for the Second Quarter and Half Year Ended 30 June 2009
• MindTree develops 'e' to SystemVerilog language migration utility
• Mirics targets ARM processor-based smartphones with FlexiTV
• Leading EDA Companies Join New ARM Fast Models Enablement Program

Headlines for Monday Jul. 27, 2009

Top Story

ARM, Chartered, IBM, Samsung, and Synopsys Collaborate to Deliver Vertically Optimized Solution for 32/28nm Mobile SoC Designs

In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor, IBM, Samsung Electronics and Synopsys today announced an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices.

• Dolphin Integration launches moDAC95-LB combining smallest silicon area and optimized Bill-of-Material
• ARM Announces Ultra Low-Power Physical IP Technology to Drive Next-Generation MCU Devices
• Magillem Releases its Verification Solution to Complement Its Existing Suite of Tools
• Xilinx Virtex-6 FPGAs Enable Highest PCIe Bandwidth for Mainstream Applications With Compliant PCI Express 2.0 Endpoint
• Altera Speeds Development of High-Performance 3-Gbps Applications With Arria II GX Development Kit
• FPGA startups stare down giants and ghosts
• Evatronix Releases JPEG 2000 Image Compression Encoder Optimized for FPGA Designs
• Samsung and Intrinsity Jointly Develop the World's Fastest ARM Cortex-A8 Processor Based Mobile Core in 45 Nanometer Low Power Process
• Kilopass Lowers Manufacturing Cost With ROM Conversion Option
• TSMC and Global Unichip Collaborate On Silicon Proven SiP Solution in TSMC Reference Flow 10.0
• Chips&Media and Innofidei Unveil New Chip Design for CMMB in China Market
• Agnisys announces an innovative tool for Verification Management and Requirement Tracking
• University of Edinburgh Develops an Advanced Research Processor based on the ARC600 Architecture
• Virtutech Announces Simics Full-System Checkpointing for SystemC Based Transaction-Level Modeling
• Atmel Standardizes on DDR2 for 400 MHz, High Speed-USB-enabled ARM9-based Embedded MPUs
• SMIC 130nm Process Used in Commercial Production of DisplayLink USB Graphics Chips
• Calypto Delivers Fully Automated Sequential Optimization Flow for High-performance IP Blocks
• MediaTek Deploys CoWare Solutions to Improve Product Development Cycle

Headlines for Friday Jul. 24, 2009

Top Story

Atmel Introduces the AT697F Radiation-Hardened SPARC V8 Processor for Space Missions

Atmel® announced today a new radiation-hardened SPARC® processor for space applications, the AT697 Revision F delivering 90 MIPs at 100 MHz over full temperature and voltage ranges for only 0.7W.

• Grace announces a new cost-effective platform of 0.18um OTP for speech IC and micro controller
• Faraday Reported 2009 Second Quarter Results
• Silicon Image Reports Second Quarter 2009 Financial Results
• Denali Expands PureSpec Solution for Predictable Protocol Verification
• Rambus Reports Second Quarter Earnings
• Lattice Semiconductor Reports Second Quarter 2009 Financial Results

Headlines for Thursday Jul. 23, 2009

Top Story

Evatronix And Soft-Mixed Signal Announce USB 2.0 Total Solution

Evatronix SA and Soft Mixed Signal announced today the availability of the complete USB 2.0 solution that integrates USB 2.0 Controller IP from Evatronix and the USB 2.0 PHY IP from Soft Mixed Signal.

• Six Early Adopters Select USB 3.0 Verification IP From Denali Software
• Nangate Releases a New Version of the 45nm Open Cell Library
• Austereo licenses audio IP core portfolio from Coreworks including SPDIF, I2S/LJ/RJ serial interfaces and asynchronous sample rate converter for use in radio broadcasting equipment
• Validity Sensors Licenses Two Tensilica Processors for High-Volume Fingerprint Sensors
• Ralink Employs MIPS32 74K Processors in New 802.11n Dual Band WLAN AP/Router SoC

Headlines for Wednesday Jul. 22, 2009

Top Story

Silicon Image Introduces New IP Core Product Family Supporting HDMI(R) 1.4 Features

Silicon Image today announced that it is expanding its market-leading family of HDMI(R) semiconductor intellectual property (IP) cores to include transmitter and receiver IP cores that incorporate features of the recently announced HDMI Specification Version 1.4.

• MOSAID Now Sampling HLNAND Flash Memory Semiconductor Chip and Module
• The business of IP: it ain't a bake sale
• Silicon Image Introduces First Port Processor With 3D Over HDMI Capability
• Samsung First to Begin Mass Producing 2-Gigabit DDR3 Using 40nm Class Technology
• TSMC Extends Design Methodology Leadership to 28nm with Reference Flow 10.0
• OVM World Collaborates on Accellera's Industry Solution for VIP Interoperability
• True Circuits Attends DAC, Features Complete Line of PLL and DLL IP

Headlines for Tuesday Jul. 21, 2009

Top Story

Chips&Media Delivers the Latest Full HD Codec IP Core Coda8550

Chips&Media today announced that its new High definition multi-standard video IP core Coda8550. Coda8550, the first IP of the next generation of Chips&Media’s advanced Coda8 series, delivers full HD(1080p) encoding capability at 30fps under 200MHz clock frequency.

• Key ASIC Collaboration to Expand Its ASIC Products and Licenses PowerPC
• Pigeon Point Systems Delivers First TCA Management Controller Solution with Advanced In-Shelf LAN Attachment
• Arasan Chip Systems Releases SuperSpeed USB 3.0 Software Stacks
• Virage Logic Offers Broadest Portfolio of Embedded Non-Volatile Memory (NVM) Solutions at TSMC
• TSMC Launches Unified Physical Verification Format for Advanced Process Technologies

Headlines for Monday Jul. 20, 2009

Top Story

Synopsys' New DesignWare IP Slashes Power in Datapath Circuits

Synopsys today announced the DesignWare® minPower Components, a new IP product that is an integral part of the Synopsys Eclypse™ Low Power Solution. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.

• Report: India to pursue homegrown microprocessor design
• NXP Successfully Deploys Integrated CoWare and ARM Cortex Processor-based Solution in its Virtual Prototyping Environment
• Calsoft Becomes Tensilica Software Design Center, Supporting Next-Generation Video/Audio and Security Oriented Application Designs
• Evatronix IP successfully implemented by HAPA AG to support their printer controllers
• Virage Logic Receives Letter of Reprimand From NASDAQ Department
• CoFluent Design Closes the Modeling GAP for Virtual Platforms
• SiliconXpress Receives Series A Funding
• Siemens Uses CoFluent to Create Models for Virtual Platform Simulation
• Sequence Launches PowerArtist-XP - Industry's First Automatic, Fully Integrated RTL Design For Power Platform

Headlines for Thursday Jul. 16, 2009

Top Story

Chartered Begins Production Ramp of Enhanced 65nm Low-Power Process; Improves Power Utilization by 30-50 Percent

Chartered today announced the general availability of an enhanced version of its 65-nanometer (nm) low-power (LP) process, called 65nm LPe. The process is also supported by a robust range of IP specifically optimized for the lower leakage capabilities.

• SeaSolve Software Inc' Automated Manufacturing Test Solution accelerates ZigBee time to market
• Study: FPGAs to grow faster than broader IC market
• EDA Consortium Reports Industry Revenue Down in First Quarter 2009
• Cadence Introduces First TLM-Driven Design and Verification Solution to Increase Engineering Productivity over RTL-based Flows
• Xilinx Announces First Quarter Fiscal 2010 Results
• NetLogic Microsystems and TSMC Collaborate on Industry-Leading 40nm Technology for Next-Generation Knowledge-based Processors and 10/40/100 Gigabit Physical Layer Solutions

Headlines for Wednesday Jul. 15, 2009

Top Story

Synopsys Accelerates Development of System-On-Chip Designs With Complete IP Solution for PCI Express 3.0

Synopsys today announced its complete DesignWare® IP solution for PCI Express® (PCIe®) 3.0 consisting of digital controllers, PHY and verification IP. Synopsys' DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-chips (SoCs) for high-performance enterprise computing applications.

• EdXact and Altos Partner to Improve IP Characterization Throughput
• Syntill8 to offer Mentor Graphics' M8051 Microcontroller IP and Support Services
• nSys Demonstrates Verification IP for PCIe 3.0 at the PCI-SIG DevCon 2009
• OneSpin's New Debug Automation Technology Boosts Formal Assertion-Based Verification Productivity
• Altera Announces Second Quarter Results Sales up 6 Percent from Prior Quarter
• EVE Ushers in New Era for Hardware-Assisted Verification with Launch of One-Billion Gate Emulator
• U.S. Patent And Trademark Office Rejects Additional Patent Claims That Rambus Is Asserting Against NVIDIA

Headlines for Tuesday Jul. 14, 2009

Top Story

More than 30 fabs to close in '09, says analyst

By the time it's all said and done, more than 30 semiconductor fabs will shut their doors this year as chip companies cut capacity in response to the downturn, according to Christian Gregor Dieseldorff, senior analyst and director of market research for the SEMI trade group.

• CAST Releases H.264 IP Core for Highest Quality HD Video Compression
• Faraday Launches Its Low-leakage Memory with Up to 90% Leakage-reduction
• Duolog's Weaver breaks the SoC integration barrier
• Satin IP Technologies, Toppan Photomasks and XYALIS Partner to Improve Design for Mask Manufacturing

Headlines for Monday Jul. 13, 2009

Top Story

MIPS Technologies Announces Planned Retirement of CEO John Bourgoin; Launches Search for Successor

MIPS Technologies today announced that long-time President and CEO John Bourgoin intends to retire at the end of the calendar year. The Company's board of directors plans to begin an immediate search for a successor, which is expected to take three to six months.

• MOSAID Sues IBM for Patent Infringement
• Renesas Technology Halves SiP Design Time with SiP Top-Down Design Environment
• Altera's Stratix IV GX FPGAs Deliver Unprecedented Performance for Sumitomo Electric Industries' LDPC System
• Actel's Mixed-Signal Power Manager Provides Complete Graphical Design Approach for Fusion Mixed-Signal FPGAs
• Blue Wonder Communications to Develop LTE Baseband IP Using Multiple Optimized Tensilica Dataplane Processors
• Chartered Offers 65nm RF Platform to Enable Single-Chip Wireless Applications
• Satin IP Technologies Helps STMicroelectronics Achieve IP Design Quality Closure
• Jasper Design Automation Introduces Multi-Proof JasperCore For Powerful, Scalable Formal Verification Deployment
• Actel Now Shipping the Fusion Advanced Development Kit
• Oasys Design Systems Revolutionizes Synthesis for 20M+ Gate Designs

Headlines for Friday Jul. 10, 2009

Top Story

Analysis: Intel slowly gears up for system-on-chips

Intel Corp. isn't giving much detail on its two-year old initiative to become a systems-on-chip supplier, but interviews with executives and analysts show the company is making gradual progress laying the foundations to build competitive SoCs for cellphones, TVs, videogame consoles and communications gear.

• TSMC June 2009 Sales Report
• Avery Design Systems Announces Support for PCI Express 3.0 Verification IP

Headlines for Thursday Jul. 09, 2009

Top Story

NXP and TSMC Deliver Industry's First 45nm Single-Chip Digital TV Platform

Featuring NXP’s PNX85500 processor, built on TSMC’s 45nm Low Power (LP) process technology, the NXP TV550 digital TV platform is a production-ready reference design that reduces time-to-market with a major step forward in functional integration for system cost down.

• NXP CoolFlux BSP's 12-bit computation has pros and cons for low-power baseband
• InSilica Inc. Licenses Beyond Semiconductor's BA22 Processor
• SMSC Announces Agreement to Acquire Tallika
• Gennum Debuts PCI Express 3.0 IP, Showcases Bridging Solutions for HD Video at PCI-SIG
• Sital releases a PCI Interface IP core for the Aerospace market sector

Headlines for Wednesday Jul. 08, 2009

Top Story

UMC denies 65-nm yield issues

UMC Tuesday (July 7) denied a report that it experienced yield problems on its 65-nm process and said some isolated problems in meeting customer requirements were the result of tight capacity due to customer rush orders.

• ARM Mali-SVG-t Software for 2D Graphics Rendering Incorporated into Range of Samsung Mobile Phones
• Mentor Graphics Delivers Hardware-Assisted Solution for the Accelerated Verification of Serial-ATA II Products
• L&T Infotech reduces Time-to-Market for OEMs through TI's OMAP3530 Reference Board

Headlines for Tuesday Jul. 07, 2009

Top Story

ARM Maintains Lead Over MIPS and Power Architecture in the Battle for the Digital Home

Analysis of findings from Semicast’s Embedded Processing Service shows that ARM maintained its position as the leading architecture for embedded processors in digital home applications in 2008, ahead of MIPS and Power Architecture.

• Atrenta Collaborates With Sonics and Denali on a 1Team-Genesis Reference Flow to Accelerate SoC Assembly
• Sarnoff Europe Becomes Sofics, Announces New System-Level ESD Solutions for High-Voltage ICs
• Faraday Monthly Sales Report -- June 2009
• MIPS Technologies and EE Solutions Bring MIPS(R) Architecture to Semiconductor Companies across China and Taiwan
• MediaTek Licenses ARM Mali-400 MP Graphics Processing Unit
• New MPEG LA MPEG-2 License Agreement Offers Extended Coverage at Reduced Royalty Rates
• Xilinx mum on supply glitch as speculation swirls

Headlines for Monday Jul. 06, 2009

Top Story

Dolphin Integration launches the BTF upgrade of its standard cell offering SESAME for 130 nm

Dolphin Integration continues their steady enhancement of the proprietary RCSL (Reduced Cell Stem Library) with the High Density stem HD-BTF for TSMC 130 nm G processes. Highly Dense and endowed with “Back-Tracking Freedom”, HD-BTF incorporates the latest architectural innovations from Dolphin Integration replacing classical flip-flops with their “spinner cell”.

• CEVA Collaborates with Tessera to Demonstrate Embedded Image Enhancement Technologies on MM2000 Portable Multimedia Platform
• Innovasic Semiconductor Announces the Availability of Pin-Compatible 80C186XL and 80C188XL Embedded Processors
• Tieto Signs Long-Term Agreement to Deploy OneSpin Solutions' Formal Assertion-Based Verification Solution

Headlines for Friday Jul. 03, 2009

Top Story

CEO: CSwitch halted operations, seeks buyer

As had been rumored, programmable logic startup CSwitch Corp. has ceased operations and is looking to be acquired, the company's top executive confirmed Friday (July 3). CSwitch President and CEO Doug Laird told EE Times that investors made the decision to temporarily halt operations sometime within the last few weeks.

Headlines for Thursday Jul. 02, 2009

Top Story

TSMC Unveils First Commercial 65-Nanometer Multi-Time Programmable Non-Volatile Memory Technology

TSMC today announced the foundry segment’s first functional 65-nanometer (nm) multi-time programmable (MTP) non-volatile memory (NVM) process technology. The technology incorporates process-qualified MTP IP blocks jointly developed with Virage Logic.

• Xilinx Updates June Quarter Guidance
• The ESL battle for hearts and minds
• Altair Semiconductor Successfully Integrates TurboConcept turbo-code IP Cores into its LTE Baseband Processor Product Line
• Initio Corp. Takes an ARC License Targeting Rapid-Growth USB 3.0 and Solid State Disk Controller Markets
• Indian design firms see uptick when recession ends
• Panavision Imaging and Tower Semiconductor Announce Production of World's Fastest Single Port Re-Configurable Linear Image Sensors

Headlines for Wednesday Jul. 01, 2009

Top Story

NSCC Launches First AVS SD Decoder Optimized For The ARM Cortex-A8 Processor With NEON Technology

ARM and NSCC today announced that NSCC has successfully developed the first AVS Standard Definition (SD) decoder optimized for the ARM® Cortex™-A8 processor with NEON™ technology. The AVS (GB/T GB/T200090.2) is the second generation of source coding/decoding standard developed by the AVS Workgroup (Audio and Video Coding Standard Workgroup of China).

• Cosmic Circuits tapes out 40nm Mixed Signal Test Chip
• Motorola Joins Via Licensing Joint Licensing Program for Near Field Communications
• LogicVision's Memory BIST & Automated Diagnosis Solutions Included by TSMC in Its Advanced Embedded Memory Development Program and QA Flow
• DensBits Selects ARC Storage to Silicon for Next Generation Multi-Bit Per-Cell Flash Technology
• Virage Logic Expands Presence in India to Serve Growing Market Demand for Broad IP Portfolio
• Synopsys MVSIM Adopted for Low Power Verification of STw8500 Mobile SoC Platform