D&R Headline News (December 2009)

Headlines for Wednesday Dec. 30, 2009

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Faraday to transfer its IP Business to Innopower

Innopower, a wholly owned subsidiary of Faraday Technology, today announced, effective immediately, that it has been granted as the sole IP distributor of Faraday. Innopower will promote Faraday IP solutions in world-wide region and provide the front-line support for customers.

• MIPS Technologies CEO John Bourgoin Confirms Year-End Retirement
• Realtek Licenses Wide Range of MIPS32 Pro Series Cores to Develop High-Performance SoCs
• Analysis: To-do-list for the next MIPS CEO
• Digital Blocks Supports the AMBA Interconnect on Xilinx FPGAs with its portfolio of AXI / AHB / APB IP Cores

Headlines for Tuesday Dec. 29, 2009

• Sequans Incorporates Industry-Leading MIMO Decoder in LTE Product Line

Headlines for Monday Dec. 28, 2009

• Infineon Reaches Agreement to Settle Legal Dispute with Fairchild
• Qualcomm Announces Leadership Changes

Headlines for Tuesday Dec. 22, 2009

• FineArch licenses Cosmic Circuits' Analog IP
• Ukalta Engineering Announces Ultra-Compact AWGN IP Library

Headlines for Monday Dec. 21, 2009

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Taiwan's Magic Pixel Licenses MIPS(R) Processor IP for Advanced Multimedia Applications

MIPS Technologies today announced that Magic Pixel has licensed the MIPS32(R) 24KEc(TM) and 4KEc(R) Pro Series(R) processor cores for development of next-generation digital photo frames (DPFs) and other portable multimedia applications.

• Aldec(R) Releases RTL Simulator with Enhanced Assertions and Xilinx(R) SecureIP Support
• Gartner Says Worldwide Semiconductor Revenue Declined $29 Billion in 2009
• TowerJazz Revises Fourth Quarter Guidance
• GigOptix Receives $4.5M Federal Funding for Polymer based Integrated Photonic Transceiver under the 2010 Department of Defense Appropriations Bill
• SIG Introduces Bluetooth Low Energy Wireless Technology, the Next Generation of Bluetooth Wireless Technology

Headlines for Friday Dec. 18, 2009

• ATIC's Acquisitation of Chartered Becomes Effective Today

Headlines for Thursday Dec. 17, 2009

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MIPS Technologies and Tensilica Team to Accelerate SOC Design Activity on Android(TM) Platform; Plan Joint Demos at CES

MIPS Technologies and Tensilica today announced they are working together to accelerate SOC (system-on-chip) design activity on the popular Android platform. Together, MIPS and Tensilica will help companies speed the design of new home entertainment and mobile consumer products based on Android.

• Plurality Secures Second Round of $12 Million Dollars From Japan-Based Investors
• eSilicon Takes Achronix 1.5 GHz FPGA Design to Production
• Chartered Begins Next Phase of Equipment Move-In at Fab 7 in Support of Planned Capacity Expansion for Leading-Edge Processes
• On2 and Google Announce Exchange Ratio for On2 Merger

Headlines for Wednesday Dec. 16, 2009

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Aptina and eASIC Announce High Definition H.264 Reference Design

Aptina and eASIC today announced the immediate availability of a H.264 High Definition (HD) reference design that is capable of supporting up to 720p/30fps rates. The HD H.264 reference design is built using Aptina’s MT9D131 HD image sensor with eASIC’s eDV9200 low cost HD H.264 CODEC.

• STMicroelectronics Unveils High-Performance System-on-Chip for Next Generation of Integrated Broadcast and Broadband-Internet Digital TVs
• CoWare and Tensilica Deliver Software Development Solution for Multi-Core Tensilica-Based Platforms
• eSilicon Signs Multi-Year Agreement with Synopsys
• Macraigor Systems Provides On-Chip Debug Solutions with Eclipse Ganymede/Galileo Platform and Full GNU Toolset Support for ARM Cortex-A8 Processors

Headlines for Tuesday Dec. 15, 2009

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Silicon Image Introduces New 4K and 3D H.264 Digital Video Decoder IP Core

Silicon Image today announced the newest member of its IP core family, the cineramIC™ 4K and 3D H.264 digital video decoder. With its high performance, low cost and high-quality video imaging, the cineramIC IP core can be integrated into System-on-Chips (SoCs) for next-generation digital TV (DTV), set-top-box (STB) and camcorder applications, as well as professional video editing, broadcast, medical and surveillance FPGA applications.

• New Algorithmic Acceleration System Features a Baker's Dozen of the Next Generation Spartan 6 FPGAs
• Counterpoint:With MIPS still growing, battle isn't over
• Arasan Chip Systems Announces Innovative SD 3.0 / eMMC 4.4 Card Controller IP
• Virage Logic Introduces the Ultra Compact and Low Power ARC(R) 601 32-Bit Microprocessor Core
• Crack Semiconductor's CS1024-RSA Sets New RSA Compute-Offload Performance Standard
• CoWare Joins ARM Solution Center for Android
• Rambus Acquires Patented Innovations and Technology from Global Lighting Technologies
• Atmel Highly-Integrated Cortex-M3-based Flash MCUs Improve Impedance Matching and Lower Power Up to 50 Percent
• Buffalo Licenses WiLAN Wireless Technologies

Headlines for Monday Dec. 14, 2009

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CEVA and Gennum's Snowbush IP Group Partner to Deliver Complete SAS 2.0 IP Solution for Embedded Storage Applications

CEVA and Snowbush today announced that they have partnered to deliver a complete Serial Attached SCSI (SAS) 2.0 IP solution optimized for embedded storage applications. The integrated offering combines Snowbush silicon-proven 6.0Gbps PHY IP integrated with CEVA's SAS 2.0 Controller IP, offering the industry's most mature and feature rich SAS 2.0 IP solution.

• Magma Announces SiliconSmart ACE -- New Standard in IP Characterization for 28 nm and Below
• Analog Devices Mixed-Signal Products in Production with Kilopass' Embedded Non-Volatile Memory
• Lattice Releases Development Platform for SERDES and Video Clock Distribution
• VT Silicon Selects TowerJazz for World's First Fully Integrated 4G RF Front End IC
• NXP Introduces Advanced 3DTV Processor

Headlines for Friday Dec. 11, 2009

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Interview: ARM wants every MIPS socket

As recently as five years ago, ARM's competitors included a host of IP processor companies such as MIPS, ARC and Tensilica. Now, like it or not, the field of serious processor competition has dramatically narrowed to, well, ARM vs. Intel Corp.

• Sigasi Announces Production Release and Pricing for its IDE for VHDL
• DOLPHIN Integration moving ahead towards Assertion-Based Verification with SLASH
• Court Denies Audiovox Motion to Renew/Reargue MPEG LA's Right to Audit
• TSMC November 2009 Sales Report

Headlines for Thursday Dec. 10, 2009

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Denali Announces State-of-the-Art GHz DDR PHY Technology

Denali today revealed a new phase PHY technology for DDR SDRAM physical interfaces, delivering memory system performance up to 1066 MHz clock speeds (or DDR-2133 data rates) on 65-nanometer foundry process nodes or lower.

• Avalon Announces Working 100GE over OTN Transponder Application
• Carbon Further Expands ARM IP Library
• Maia EDA Launches New Automated Verification Tool
• GDA Technologies Adds PowerPC(R) 440T90 Hard Macro to Its Portfolio Using TSMC 90nm Process Technology
• eInfochips acquires nGIN Technologies
• HyperTransport Consortium Extends Signal Transmission Distance by 6x and Provides Flexible Options With New Connector Specifications
• Aldec Adds DO-254/ED-80 Library to HDL Design Rule Checker
• eSilicon Names Virage Logic as Supplier of the Year

Headlines for Wednesday Dec. 09, 2009

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Mixel first to market with Unified MIPI/MDDI PHY IP solution

Mixel announced today the availability of the first MIPI/MDDI unified PHY IP solution. The IP combines a MIPI D-PHY compliant with revision 1.0 of the MIPI standard, with an MDDI-PHY compliant with revision 1.2 of the MDDI standard.

• Analyst: FPGA firms to outgrow semi industry by 2X
• GigOptix Reduces System-on-Chip Risk and Slashes Development Costs With Its New CX7800 65nm Hybrid ASIC
• European Commission Accepts Rambus Commitments in Final Settlement
• Panelists look at IP quality versus design productivity
• Imagination Technologies Group plc - Interim Results for the six months to 31 October 2009.
• New Xilinx Virtex-6 and Spartan-6 FPGA Connectivity Development Kits Include Northwest Logic DMA Engine IP
• Ubicom Expands Long-Term Relationship with Denali By Adopting Its Predictable Protocol Verification Solution
• IPextreme Teams Up with Infineon To Bring Complete Bluetooth IP Solution to Market
• Arasan Chip Systems' Participation at IP & ESC'09, Grenoble, France Captures Evolution of IP Business to Total IP Solutions

Headlines for Tuesday Dec. 08, 2009

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New Xilinx Connectivity, Embedded, and DSP Kits Enable Increased Productivity and Innovation for System-on-Chip Designs

Xilinx, Inc. today announced six new development kits as part of its Targeted Design Platforms for enabling developers to focus on innovation and differentiation when designing with FPGAs.

• Xelic Announces Availability of 40G Enhanced Forward Error Correction Core for Optical Transport Networking Applications
• Xilinx Raises December Quarter Sales Guidance
• Sarnoff Releases Acadia II SoC Development Platform
• X-FAB Launches Strategic Third-Party IP and Design Partner Network; Expands In-House Technical Service Support
• Mentor Graphics Expands Questa Multi-view Verification Components Library to Support a Larger Set of Standard Protocols
• Tensilica Delivers New Design Flow Support for Synopsys' Galaxy Implementation Platform Technologies
• Altera Ships Stratix IV E FPGA Development Kit Featuring a 530K Logic Element FPGA

Headlines for Monday Dec. 07, 2009

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Arteris Raises $9.7M as Qualcomm and ARM Join Existing Investors behind Network-on-Chip (NoC) Pioneer

Arteris announced today that it has raised the first tranche of a strategic investment round totaling $9.7 million from a group of investors led by Qualcomm Incorporated and including ARM.

• On2 Technologies Provides Update On Its Proposed Merger With Google
• Wind River Launches Commercial Android Platform
• S3 Assists Siano To Develop Mobile Digital TV Chips
• Analysis: strategic versus ROI-driven VC
• Discretix joins ARM Solution Center for Android
• CEVA Unveils Industry's First C-Based Application Optimization Toolchain for Licensable DSPs
• DapTechnology's FireLink 1394b LLC IP Core Enhances PixeLINK's Firewire Vision
• K-micro and Anritsu collaborate to develop first test tool and methodology to analyze 10G EPON chips
• Top EDA Companies Endorse Tensilica's Pin-Level SystemC Models
• Tensilica Announces Enhanced Tools for Dataplane Processor Design and Software Development
• IXYS Announces Acquisition of Zilog
• Genesys Logic Will Display USB 3.0 Products at CES 2010

Headlines for Friday Dec. 04, 2009

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Panelists question fabless model viability

Is fabless still fabulous? In a panel session at the IP-ESC 2009 Conference this week in Grenoble, France, panelists discussed the evolution of semiconductor business models and confronted views on whether the fabless model is dead or alive and kicking.

• Dolphin Integration promotes a design methodology ensuring High-Yield circuits despite Mismatch
• Is design and reuse an impossible dream, ask panelists
• IP providers, SoC told to go for compromises
• Samsung to Offer 1 Gigabit XDR DRAM
• SiTune Corporation Secures Series B Financing with Greenlane Investments LLC

Headlines for Thursday Dec. 03, 2009

• ARM Cortex-M0 Processor - Fastest Licensing ARM Processor
• Ittiam Unveils 60ms Ultra Low-Latency Streaming Systems for High Definition Video
• Evatronix Usb-if verified USB 3.0 Device controller achieves over 430 mb/s
• Evatronix Announces Formation Of The Technical Advisory Board
• Altera's Stratix IV FPGAs to Power XDI's dbX Analytics Appliance
• Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2009
• Viosoft Announces Android Adoption Kit for MIPS-Based™ Digital Multimedia Designs

Headlines for Wednesday Dec. 02, 2009

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Novocell Semiconductor Announces the Development Of A Multi-Time Programmable Antifuse Bit Cell

Novocell today announced the development of 2nTP, a new multi-time programmable (MTP) technology that allows the programming of its one-time programmable (OTP) antifuse bit cell up to eight (8) times. 2nTP can be configured as a two, four, or eight times write, and it is based on the NovoBlox™ bit cell, a non volatile memory (NVM) already proven at leading foundries.

• Jointwave H.264 IP solution at both InterBEE 2009 and ET 2009 Show
• MindTree's Real-Time Video Stitching Algorithm Enhances Field of View

Headlines for Tuesday Dec. 01, 2009

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ARM exec gives hints for IP business model optimization

In a keynote at the IP-ESC 2009 Conference this week in Grenoble, France, Eric Schorn, vice president of marketing, processor division ARM Ltd, compiled a How-To list of basic steps to optimize IP business models and better deliver value to the customer.

• SiliconBlue Technologies is the First New FPGA Company to Ship in Production Volume in 20 Years
• EVE's Latest Emulator Offers the Lowest Cost of Ownership in the Industry
• Novelics, Chips & Media, and Posedge Join IPextreme Constellations
• Synfora Adds Support For Next Generation Xilinx Virtex-6 And Spartan-6 FPGA Devices To PICO Algorithmic Synthesis Tool
• SpringSoft and Magma Validate Full Interoperability of Custom Chip Design Tools with TSMC 65nm iPDK
• Sonics Offers Free Evaluation for Designers of Sonics Network for AMBA Protocol Solution
• Altera Updates Fourth Quarter Guidance Sales Expectations Move Upward