D&R Headline News (December 2017)

Headlines for Thursday Dec. 28, 2017

• Arastu Systems enhances outreach with the establishment of its Global Sales Channel

Headlines for Friday Dec. 22, 2017

Top Story

Chipus Microelectronics receives ISO 9001 certification

Focused and specialized in utra low power IC Design, Chipus Microelectronics recently received the ISO 9001:2015 certification. With an important part of its activity concentrated in the international market, especially in the USA, Europe and Asia, the company today has more recognition on the quality of the solutions delivered to its customers.

Headlines for Thursday Dec. 21, 2017

Top Story

UMC Announces Availability of 40nm SST Embedded Flash Process

UMC today announced the availability of the company’s 40nm process platform that incorporates Silicon Storage Technology’s (SST) embedded SuperFlash® non-volatile memory. The newly available 40nm SST process features a >20% reduction in eFlash cell size and 20-30% macro area over UMC’s mass production 55nm SST technology.

• NXP and Baidu Partner on Apollo Open Autonomous Driving Platform
• Rambus Renews Patent License Agreement with Panasonic
• The Deals and No Deals that shaped 2017
• QuickLogic to Demonstrate Sensor Processing and eFPGA Solutions at CES 2018

Headlines for Wednesday Dec. 20, 2017

• Khronos Group Releases NNEF 1.0 Standard for Neural Network Exchange

Headlines for Tuesday Dec. 19, 2017

Top Story

Intel Unveils Industry's First FPGA Integrated with High Bandwidth Memory Built for Acceleration

Intel today announced the availability of the Intel® Stratix® 10 MX FPGA, the industry’s first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2).

• Broadcom Ships Tomahawk 3, Industry's Highest Bandwidth Ethernet Switch Chip at 12.8 Terabits per Second
• X-FAB Introduces New Low-Power eFlash Block Optimized for Energy Harvesting & IoT Devices
• HDL Design House Launches New Website

Headlines for Monday Dec. 18, 2017

Top Story

Creonic Launches 5G Product Line with Polar and LDPC FEC IP Cores

Creonic GmbH today announced its new product line for 5G FEC (forward error correction). The product line covers LDPC decoder as well as Polar encoder and decoder IP cores for this latest 3GPP specification (3GPP Release 15).

• Inside Secure Delivers Next-generation Content Protection Solutions Extending Leadership in Device Coverage and Early-window Premium Video
• StarHub Deepens Secure Smart Nation Capabilities with Acquisition of D'Crypt
• North American Semiconductor Equipment Industry Posts November 2017 Billings

Headlines for Thursday Dec. 14, 2017

Top Story

ICE-P3 EPU Upgrade Simplifies Control Of On-Chip And External Resources To Save More Power In SoC And MCU Designs

Sonics upgraded its ICE-P3™ Energy Processing Unit (EPU), the flagship member of the ICE-Grain™ Family of EPU products, to add a new programmable Sequencer. The Sequencer enables designers of power-sensitive chips like systems-on-chip (SoC) and microcontrollers (MCU) to significantly improve control over both on-chip and external voltage and frequency resources to minimize energy consumption.

• Tortuga Logic Appoints Andrew Dauman Vice President of Engineering to Oversee Product Development, R&D
• Synopsys and Helic Deliver Unified Electromagnetic-Aware Analog and RF Custom Design Flow
• BrainChip Announces Change in Board Membership
• QuickLogic Collaborates with Mentor to Provide Seamless Design Environment for eFPGA Technology
• Achronix Wins 2017 Company of the Year Award

Headlines for Wednesday Dec. 13, 2017

Top Story

Innovative Logic USB 3.1 Gen 2 IP got Certification from USB-IF

Inno-Logic’s USB3.1 gen2 device controller along with PHY from M31 Technology again successfully passed all compliance tests and received certification from USB-IF in November 2017. Besides USB 3.1 gen 2 Controller IP, the USB 2.0 device controller IP also passed the certification test in November, 2017.

• Catena selects Thalia-DA to facilitate analog IP re-use
• SMIC and Efinix Quickly Deliver the First Quantum-Accelerated Silicon Product
• STMicroelectronics Acquires Atollic, an Embedded-Systems Company Engineering Integrated Development Environments for Arm-core-based Microcontrollers
• iC-Haus Selects Synopsys' IC Validator and StarRC for Signoff
• Truechip Successfully hosted TrueConnect 2017 - The First Annual Technical Conference
• Aldec releases re-configurable FPGA-based accelerators for High Frequency Trading applications

Headlines for Tuesday Dec. 12, 2017

Top Story

Kilopass NVM OTP IP Achieves 3-Lot Qualification on GLOBALFOUNDRIES 14nm LPP (Low Power Process) Process Technology

Kilopass Technology Inc., a leading provider of semiconductor logic embedded non-volatile memory (eNVM) intellectual property (IP), today announced that it successfully achieved a three-lot qualification on GLOBALFOUNDRIES (GF) 14nm LPP (Low Power Process) technology platform for its one-time programmable (OTP) NVM technology.

• Performance-IP, CEVA Collaborate to Accelerate DSP System Performance
• MIPI Alliance Opens Access to its MIPI I3C Sensor Interface Specification
• Microsemi and Imperas Announce Extendable Platform Kit for Microsemi Mi-V RISC-V Soft CPUs
• VESA Defines New Standard to Help Speed PC Industry Adoption of High Dynamic Range Technology in Laptop and Desktop Monitor Displays
• Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks
• Moortec to exhibit their embedded In-Chip Monitoring Subsystem IP at the REUSE 2017 Expo in Santa Clara
• $55.9 Billion Semiconductor Equipment Forecast - New Record with Korea at Top
• Synopsys Completes Acquisition of Black Duck Software

Headlines for Monday Dec. 11, 2017

Top Story

TSMC Speeds Opening of China Fab

Taiwan Semiconductor Manufacturing Co. (TSMC) said it aims to open its second fab in China earlier than originally expected in order to meet strong demand in the world’s fastest growing semiconductor market.

• Lattice Diamond Software Receives Road Vehicles Functional Safety Qualification (ISO 26262)
• Inside Secure protects Lufthansa Technik's inflight entertainment on passenger devices
• SEGGER presents RTOS, stacks, middleware for RISC-V
• Euresys Acquires Sensor to Image

Headlines for Friday Dec. 08, 2017

Top Story

Reduced Energy Microsystems Joins FDXcelerator Program to Bring RISC-V IP to GLOBALFOUNDRIES' 22FDX Technology Process

Reduced Energy Microsystems (REM) announced today that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program, and will be making RISC-V CPU IP available for GF’s 22FDX® process. Based around the open source RISC-V ISA, REM’s IP will offer a low-power core to be integrated into future SoCs to be used across a range of verticals.

• UMC Reports Sales for November 2017
• Faraday Monthly Consolidated Sales Report - November 2017
• TSMC November 2017 Revenue Report

Headlines for Thursday Dec. 07, 2017

Top Story

SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture

Microsemi today announced SiFive has joined Microsemi's new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider.

• HiSilicon Divison of Huawei licenses UltraSoC's SoC monitoring and analytics solutions
• Few Surprises as Intel, GloFo Detail Process Technologies

Headlines for Wednesday Dec. 06, 2017

Top Story

Synapse Design Strategic Growth Activity Continues with Acquisition of ACEIC

Synapse Design Inc., the leading design services partner serving Tier 1 system and semiconductor companies, today announced that they have purchased all assets including the engineering team and verification IP of ACEIC Design Technologies.

• UltraSoC and Percepio partner to offer first complete embedded analytics platform for real-time systems
• Kilopass Anti-Fuse NVM OTP IP Designed into Montage Technology Next Generation Set-Top Box Chips Targeting Emerging Market Environments

Headlines for Tuesday Dec. 05, 2017

Top Story

Arasan Announces Industry's First MIPI C-PHY HDK

Arasan today announced availability of its MIPI C-PHY[SM] HDK built using an Arasan C-PHY ASIC. The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz and D-PHY v1.2 also with speeds of up to 2.5GHz.

• For the 3rd Time, ArterisIP Appears on the Inc. 5000 list
• Think Silicon Joins SiFive's Growing DesignShare Ecosystem
• Digital Core Design introduces I3C IP Core
• Videantis and ADASENS partner to address explosive growth in intelligent automotive cameras
• Inomize is selected as Supply Chain Manager and to support the development of 3D camera and XR ASIC using TSMC 12nm FFC Technology
• Global Semiconductor Sales Increase 21.9 Percent Year-to-Year in October; Industry Forecast Revised Upward
• GUC Monthly Sales Report - Nov 2017
• IPrium offers the ModemKit for immediate wireless IP Cores evaluation

Headlines for Monday Dec. 04, 2017

• GLOBALFOUNDRIES and Ayar Labs Establish Strategic Collaboration to Speed Up Data Center Applications
• Green Hills Software Expands Automotive Integrated Cockpit Coverage to NXP i.MX 8 Families
• When Less is Moore