D&R Headline News (June 2019)

Headlines for Thursday Jun. 27, 2019

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Rambus Expands Family of CryptoManager Root of Trust Secure Silicon IP Cores

Rambus today announced the expansion of the CryptoManager Root of Trust family of products, a series of fully programmable, hardware-level secure silicon IP cores to address the security needs of applications including IoT, AI, ML, cloud, government, military and automotive. CryptoManager cores employ a siloed architecture.

• AI Startup Preps Inference Chip
• Micron Cuts Capex, Wafer Starts
• BrainChip and Socionext Sign a Definitive Agreement to Develop the Akida Neuromorphic System-on-Chip

Headlines for Wednesday Jun. 26, 2019

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MorningCore Technology License CEVA DSP for High Performance Wireless and Automotive Communication Platforms

CEVA announced today that MorningCore Technology Co., Ltd, a subsidiary of China Information and Communication Technologies Group Corp (CICT), has licensed and deployed the CEVA-XC DSP in its family of software-defined radio (SDR) processors and platforms targeting high performance 4G/5G wireless and cellular vehicle-to-everything (C-V2X) applications.

• Cadence Announces First-to-Market DisplayPort 2.0 Verification IP
• VESA Publishes DisplayPort 2.0 Video Standard Enabling Support for Beyond-8K Resolutions, Higher Refresh Rates for 4K/HDR and Virtual Reality Applications
• InAccel release world's first FPGA orchestrator
• Mentor's Veloce Strato emulation platform selected by Iluvatar CoreX for verification of AI chips and software
• Real Intent Announces 10X+ Speedup & 5X Capacity Improvement for Ascent AutoFormal Automatic RTL Verification
• NanoSemi Relies on OneSpin Automated Formal Verification Tools to Verify SystemC Designs for 5G ASICs
• Aspinity Enables 10x Less Power for Always-on Sensing

Headlines for Tuesday Jun. 25, 2019

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CEVA Introduces Fully-Integrated Wi-Fi Solution to Connect IoT Devices to the Alibaba Cloud

The turnkey solution integrates CEVA’s industry-leading RivieraWaves Wi-Fi Low Power IP together with the AliOS Things operating system on a single RISC-V CPU core, providing customers with the freedom to focus their development efforts on creating differentiation in the end application.

• SmartDV Adds New Verification IP to Support OpenCAPI Standard
• Visa to Acquire Rambus Payments Portfolio
• Arteris IP FlexNoC Interconnect Implemented in Uhnder Digital Automotive Radar-on-Chip
• Synopsys Expands Center of Excellence with Infineon to Deliver Virtualizer Development Kit for AURIX TC4x Automotive Microcontroller
• eMemory's NeoFuse Qualified on Winbond 25nm DRAM Process

Headlines for Monday Jun. 24, 2019

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UltraSoC secures £5m investment to target safety and security applications with its embedded analytics

UltraSoC today announced plans to substantially grow its worldwide operations to address emerging opportunities in the cybersecurity, high-reliability and safety-critical systems markets.

Headlines for Friday Jun. 21, 2019

• North American Semiconductor Equipment Industry Posts May 2019 Billings

Headlines for Thursday Jun. 20, 2019

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Vidatronic Licenses Power Management Unit and Analog IP to Leading Semiconductor IP Company, Arm

Vidatronic, Inc., a leading provider of analog, power management unit (PMU) and CMOS radio frequency (RF) Intellectual Property (IP) licenses, today announced that they will provide PMU and analog IP cores to multinational semiconductor and software design company, Arm, for use in their solutions.

• Western Digital Extends Openness of PlatformIO and Enhances its RISC-V Portfolio to Accelerate Data-Centric Innovation
• "Video For Machines" Using MPEG's New CDVA Standard, On Gyrfalcon's Industry Leading Chips
• ON Semiconductor Completes Acquisition of Quantenna Communications
• GLOBALFOUNDRIES Adds Industry Veteran Glenda Dorchak to its Board of Directors to Support Next Phase of Transformative Growth
• eSilicon, Samtec and Wild River Technology Offer High-Performance Communications Webinar
• Attopsemi Technology's Notification of Office Relocation

Headlines for Wednesday Jun. 19, 2019

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PCI-SIG Announces Upcoming PCI Express 6.0 Specification to Reach 64 GT/s

PCI-SIG® today announced that PCI Express® (PCIe®) 6.0 technology will double the data rate to 64 GT/s while maintaining backwards compatibility with previous generations and delivering power efficiency and cost-effective performance. The PCIe 6.0 specification is actively targeted for release in 2021.

• Acacia Communications Adopts Cadence Palladium Z1 Enterprise Emulation Platform to Accelerate Optical Networking Development
• Can Huawei Survive?
• CSEM and MIFS demonstrate world-record lows in energy consumption for a microcontroller
• Nurlink Completes First Call on Commercial NB-IoT Network with its CEVA-powered eNB-IoT SoC
• U.S. Companies Dominate Worldwide IC Marketshare

Headlines for Tuesday Jun. 18, 2019

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Astera Labs Verifies Its System-Aware PCI Express 5.0 Smart Retimer Using Avery Design Systems PCIe 5.0 Verification IP

Avery Design Systems, leader in functional verification solutions today announced that Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer.

• SiFive Enhances Silicon Hills Operations with Office in Austin, Texas
• Achronix Selects Moortec's 7nm Embedded Temperature Sensor to Optimise Performance and Reliability in its 4th Generation Speedster FPGA
• Xilinx Hits Milestone with First Customer Shipments of Versal ACAP
• Arteris IP FlexNoC Interconnect Licensed by Achronix for New Speedster7t FPGA family
• Chiplet Ecosystem Slowly Picks up Steam
• NVIDIA Brings CUDA to Arm, Enabling New Path to Exascale Supercomputing
• Telechips selects PowerVR GPU for Automotive

Headlines for Monday Jun. 17, 2019

• Moortec to Showcase its PVT Monitoring IP at TSMC China Technology Symposium
• Introducing Intel's New Network and Custom Logic Group
• Global Top Ten Foundries for 2Q19 Perform Less-than-expected Due to Sliding Demand and High Inventories, Says TrendForce
• UltraSoC joins GSA IoT Security Working Group
• Can We Believe The Hype About China's Domestic IC Production Plans?

Headlines for Thursday Jun. 13, 2019

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X-FAB and Efabless Announce Successful First Silicon of Raven, An Open-Source RISC-V Microcontroller

X-FAB Silicon Foundries, the leading analog/mixed-signal and specialty foundry, together with crowd-sourcing IC platform partner Efabless Corporation, today announced the successful first-silicon availability of the Efabless RISC-V System on Chip (SoC) reference design.

• Toshiba Selects Cadence Tensilica Vision P6 DSP as Image Recognition Processor for its Next-Generation ADAS Chip
• UltraSoC strengthens management team with appointment of CFO
• Mythic Secures $30M in New Financing and Strengthens Leadership Team

Headlines for Wednesday Jun. 12, 2019

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Synopsys Achieves ISO 9001 Certification for IP Quality Management System

Synopsys, Inc. (Nasdaq: SNPS) today announced that its IP Business Unit has achieved ISO 9001 Quality Management System certification by the British Standards Institute (BSI), one of the world's largest certification bodies.

• Everspin Enters Pilot Production Phase for the World's First 28 nm 1 Gb STT-MRAM Component
• Global Fab Equipment Spending to Rebound in 2020 with 20 Percent Growth
• IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks
• Intel to Acquire Barefoot Networks, Accelerating Delivery of Ethernet-Based Fabrics
• Magewell Selects Lattice Semiconductor ECP FPGA Family For Video Capture Devices

Headlines for Tuesday Jun. 11, 2019

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Silicon-Proven Arteris IP Ncore Cache Coherent Interconnect Implemented in Toshiba ISO 26262-Compliant ADAS Chip

Arteris IP today announced that Toshiba has taped out its next generation automotive advanced driver assistance system (ADAS) chip using the Arteris IP Ncore Cache Coherent and FlexNoC®non-coherent interconnect with the associated Resilience Package.

• Cobham Releases New Instruction Simulator for Radiation Hardened Processors
• Logic Design Solutions Introduces the first NVMe Host IP on PolarFire FPGA
• Imperas and Metrics Collaborate to Jump Start RISC-V Core Design Verification Using Open Source Instruction Stream Generator
• Space Codesign Systems Announces Support of Zynq UltraScale+ MPSoC
• Gyrfalcon's 2803 Plai Plug Development Hardware Delivers 24 TOPS/W for AI From Edge to Cloud
• HDL Design House Adds New Representative in Europe
• Marvell Extends Strategic Partnership with Arm
• intoPIX Presents the Smart Path for AV Over IP at InfoComm 2019
• Dream Chip opened new ASIC Design Center in Eindhoven, Netherlands

Headlines for Monday Jun. 10, 2019

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Andes Technology Launches RISC-V FreeStart Program with its Commercial-Grade CPU N22

Andes Technology today announces its RISC-V FreeStart program. The program offers an easy and fast way to build a solid SoC foundation on the commercial-grade RISC-V CPU core N22, available for free download. AndesCore™ N22 is an entry-level, ultra-compact, low-power and performance-efficient RISC-V CPU IP.

• TSMC May 2019 Revenue Report
• CEVA Collaborates with Ellisys to Achieve SIG Qualification for its Bluetooth 5.1 Low Energy IP
• SingMai offer universal encoding and decoding of analogue video
• UMC Reports Sales for May 2019

Headlines for Friday Jun. 07, 2019

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Silex Insight now supports 1GbE, 2.5GbE & 10GbE with their AV over IP OEM boards

Silex Silex Insight, a leading provider of AV over IP solutions, announces the extension of its family of ultra-low latency Audio/Video over IP OEM boards (called Viper), with the support of 2,5Gb and 10Gb Ethernet (in addition to 1GbE).

• GLOBALFOUNDRIES and Soitec Announce Multiple Long-term SOI Wafer Supply Agreements to Meet Accelerating Demand in 5G, IoT and Data Center
• Imperas delivers first RISC-V Simulator for new Vector and Bit Manipulation specifications to Lead Customers
• SiFive Celebrates Historic 100 Design Win Milestone
• SiFive Secures $65.4 Million In Series D Funding

Headlines for Thursday Jun. 06, 2019

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OpenHW Group created and announces CORE-V family of open-source cores for use in high volume production SoCs

A new not-for-profit global organization aims to boost the adoption of open-source processors by providing a platform for collaboration, creating a focal point for ecosystem development, and offering open-source IP for processor cores.

• ARM gets a rival as AMD licenses graphics IP to Samsung
• Efabless Collaborates with GLOBALFOUNDRIES to Enable New IP Development Models for Emerging Applications
• Communications IC Market to Again Surpass Computer IC Market
• Lattice Diamond 3.11 Software Adds Support for New MachXO3D FPGA
• GUC Monthly Sales Report - May 2019

Headlines for Wednesday Jun. 05, 2019

Top Story

Inside Secure Releases Industry's First Tool to Quickly, Graphically Create Secure Crypto Architectures

Inside Secure (Euronext Paris: INSD) today announced general availability of Whitebox Designer, its new software security tool that arms vehicle app developers, IoT device developers and OEMs with new levels of protection, reduced time to market, and simplified creation of crypto architectures.

• Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality
• First steps towards a made-in-Europe high-performance microprocessor
• Global Semiconductor Sales Decrease 14.6 Percent Year-to-Year in April; 12 Percent Decrease in Annual Sales Projected for 2019
• SolidRun and Gyrfalcon Team Up to Accelerate On-Device AI Performance with Powerful New i.MX 8M Mini SOM
• Socionext Adopts the Cadence Full-Flow Digital and Signoff Tools for 7nm Designs

Headlines for Tuesday Jun. 04, 2019

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Synopsys and GLOBALFOUNDRIES Collaborate to Develop Broad Portfolio of DesignWare IP for 12LP FinFET Process

Synopsys today announced its collaboration with GLOBALFOUNDRIES (GF) to develop a broad portfolio of DesignWare® IP, including Multi-Protocol 25G, USB 3.0 and 2.0, PCI Express® 2.0, DDR4, LPDDR4/4X, MIPI D-PHY, SD-eMMC, and Data Converters, for GF's 12-nanometer (nm) Leading-Performance (12LP) FinFET process technology.

• Achronix Chooses Rambus GDDR6 PHY IP for Next-Generation FPGA
• Synopsys Fusion Design Platform First to be Certified by Samsung Foundry for 5LPE Process with EUV Technology
• Thalia DA attracts $2m investment to grow analog IP re-use platforms
• Cadence Expands Customer-Managed Cloud Options with New Cloud Passport Partner Program
• Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
• First Quarter 2019 Worldwide Semiconductor Equipment Billings Drop 19 Percent Year-Over-Year
• Analog Bits and GLOBALFOUNDRIES Deliver Differentiated Analog and Mixed Signal IP for High-Performance Mobile and Compute Applications
• ASPEED Technology adopts M31 Technology MIPI D-PHY IP to provide global 360-degree imaging SoC solution
• Truechip Offering complimentary licenses of PCIe Gen 3 Verification IP
• Omni Design Demos Hyperon 14-bit 1.2Gsps ADC at the 2019 Design Automation Conference in Las Vegas

Headlines for Monday Jun. 03, 2019

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Infineon to acquire Cypress, strengthening and accelerating its path of profitable growth

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) and Cypress Semiconductor Corporation (NASDAQ: CY) today announced that the companies have signed a definitive agreement under which Infineon will acquire Cypress for US$23.85 per share in cash, corresponding to an enterprise value of €9.0 billion.

• AMD and Samsung Announce Strategic Partnership in Ultra Low Power, High Performance Graphics Technologies
• UltraSoC embedded analytics selected to support Wave Computing's TritonAI 64 IP platform
• Gyrfalcon offers Automotive AI Chip Technology
• Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library
• Fab Joint Venture Seen for 200 mm
• Mentor sets new software scaling benchmark for Semiconductor Design Workload on Microsoft Azure
• Intel Says EUV Ready, Challenging