RISC-V-based AI IP development for enhanced training and inference
GF Seeks Fab, ASIC Partners
Reorg focuses on financial performance
Rick Merritt, EETimes
5/14/2018 00:01 AM EDT
PALO ALTO, Calif. — The new CEO of GlobalFoundries has a charter to improve financial performance of the privately-held chip maker. Thus, Tom Caulfield is seeking partners for the company that is a distant second in a hotly competitive race to make chips.
Caulfield needs a hand building a next-generation fab, probably at 3nm, and expanding his ASIC services to attract new customers. Meanwhile, he started a reorganization geared to make the company more nimble and to hold his managers responsible for financial progress, he said in an interview with EE Times.
The new fab is probably best suited as an expansion of GF’s existing Fab 8 in Malta, New York, where it is preparing to ramp a 7nm node. Such a facility likely would need support from federal funds, but GF has other options leveraging its fabs in China, Germany and Singapore.
E-mail This Article | Printer-Friendly Page |
|
Related News
- U.S. Department of Defense Partners with GLOBALFOUNDRIES to Manufacture Secure Chips at Fab 8 in Upstate New York
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Agile Analog partners with sureCore on CryoCMOS Innovate UK project
- Key ASIC Signed LOI to Acquire Wafer FAB in The US
- Alphacore Inc.: We're partners in the GF FDX Network
Breaking News
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Creonic Introduces Doppler Channel IP Core
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
Most Popular
- Imagination pulls out of RISC-V CPUs
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- BrainChip Brings Neuromorphic Capabilities to M.2 Form Factor
- RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY