AImotive's latest aiWare3P delivers superior NN acceleration for production L2-L3 automotive AI
Latest release of aiWare3 hardware IP includes significantly better host CPU offload, lower memory bandwidth and upgraded SDK tools to enable scalable, low-power, low latency solutions up to 100+ TOPS
BUDAPEST, Hungary, Dec. 19, 2019 -- AImotive, one of the world's leading suppliers of modular automated driving technologies, announced that it has begun shipment of the latest release of its acclaimed aiWare3 NN (Neural Network) hardware inference engine IP. The aiWare3P IP core incorporates new features that result in significantly improved performance, lower power consumption, greater host CPU offload and simpler layout for larger chip designs.
"Our production-ready aiWare3P release brings together everything we know about accelerating neural networks for vision-based automotive AI inference applications;" said Marton Feher, senior vice president of hardware engineering for AImotive. "We now have one of the automotive industry's most efficient and compelling NN acceleration solutions for volume production L2/L2+/L3 AI."
Each aiWare3P hardware IP core offers up to 16 TMAC/s (>32 TOPS) at 2GHz, with multi-core and multi-chip implementations capable of delivering up to 50+ TMAC/s (>100 INT8 TOPS). The core is designed for AEC-Q100 extended temperature operation and includes a range of features to enable users to achieve ASIL-B and above certification. Key upgrades include:
- Enhanced on-chip data reuse and movement, scheduling algorithms and external memory bandwidth management
- Improvements ensure that 100% of most NNs execute within the aiWare3P core without host CPU intervention
- Range of upgrades reducing external memory bandwidth requirements
- Advanced cross-coupling between C-LAM convolution engines and F-LAM function engines
- Physical tile-based microarchitecture, enabling easier physical implementation of large aiWare cores
- Logical tile-based data management, enabling efficient workload scalability up to the maximum 16 TMAC/s per core
- Significantly upgraded SDK, including improved compiler and new performance analysis tools
The aiWare3P hardware IP is being deployed in L2/L2+ production solutions, as well as studies of advanced heterogeneous sensor applications. Customers include Nextchip for their forthcoming Apache5 Imaging Edge Processor, and ON Semiconductor for their collaborative project with AImotive to demonstrate advanced heterogeneous sensor fusion capabilities.
As part of their commitment to open benchmarking using well-controlled benchmarks reflecting real applications, AImotive will be releasing a full update to their public benchmark results in Q1 2020 based on the aiWare3P IP core.
The aiWare3P RTL will be shipping from January 2020.
|
AImotive Hot IP
Related News
- AImotive's aiWare3 Hardware IP Helps Drive Autonomous Vehicles To Production
- Neural Network Inference Engine IP Core Delivers >10 TeraOPS per Watt
- Fractile Licenses Andes Technology's RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
- Siemens simplifies development of AI accelerators for advanced system-on-chip designs with Catapult AI NN
- Veriest Solutions and Neuronix AI Labs Collaborate for Neural Network Acceleration
Breaking News
- Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
- Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution
- S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development
- PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
Most Popular
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- Cadence to Acquire Arm Artisan Foundation IP Business
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New Breakthroughs in China's RISC-V Chip Industry
- Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |