55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
TSMC Plots the Process Course to Its Next "Generational Node"
By Brian Santo, EETimes (August 25, 2020)
Even as it ramps up production on its N5 process, Taiwan Semiconductor Manufacturing Co. (TSMC), at its annual Technology Symposium, introduced its N4 process, which it said is scheduled to come online in late 2021, with volume production in 2022. Anticipating the inevitable question, the company also provided some details about its subsequent N3.
Before getting into the intermediate future, TSMC offered some near-future news. The company revealed a plan to implement an enhanced version of N5, called N5P, in 2021. The N5 refinement will provide an additional 5 percent speed gain and 10 percent power improvement over N5, TSMC said.
N4, the company promised at its annual Technology Symposium, will be a “straightforward migration” from, and an extension of, N5, of course with some performance, power and density enhancements. On the production side, TSMC said it will be able to reduce the number of mask layers somewhat. On the design side, the company said it will have design rules, SPICE and IP compatible with N5.
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