SEGGER and Cadence team up to add native J-Link support for Cadence Tensilica cores
October 4, 2022 -- SEGGER, a leading supplier of software libraries, development tools, debug probes and flash programmers, today announced native J-Link debug probe support for select instances of the Cadence Tensilica Processor IP, a portfolio of configurable and extensible controllers and DSPs.
The Cadence Tensilica cores supported in the first implementation phase are the Tensilica Xtensa LX7 CPU, a number of Tensilica HiFi DSPs (HiFi 4, HiFi 3z, HiFi 3, and HiFi 1), as well as the Tensilica Fusion F1 DSP. The latest hardware versions of all commercial SEGGER J-Link models (J-Link BASE, J-Link PLUS, J-Link ULTRA+, and J-Link PRO) now support high-speed download and debugging of these cores via JTAG and SWD.
“The SEGGER J-Link is the most widely used line of debug probes in the market,” says Ivo Geilenbruegge, Managing Director of SEGGER. “J-Links have provided solid value to embedded development for over 15 years. Unparalleled performance, an extensive feature set, a multitude of supported CPUs, and compatibility with popular development environments all make J-Link an unbeatable choice. We’re happy to add Cadence Tensilica IP to the list of supported cores.”
“The drive to push intelligence further out to the edge means that more and more MCUs and SoCs contain our Tensilica CPU and DSP IP,” said George Wall, Group Director of Product Marketing for Tensilica Xtensa Processor IP at Cadence. “The new SEGGER implementation enables us to use the J-Link GDB Server as a native J-Link driver in our Tensilica Xplorer Integrated Development Environment (IDE), resulting in a significant performance increase. As a result, customers will be able to debug their firmware running on Tensilica cores more quickly.”
The Cadence Tensilica core support has already been added to the J-Link software pack, which is available for download from the SEGGER website.
For more information on J-Link, please visit:
https://www.segger.com/products/debug-probes/j-link/
|
Related News
- SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe
- Cadence Tensilica HiFi IP Accelerates AI Deployment with Support for TensorFlow Lite for Microcontrollers
- New Cadence Tensilica ConnX B20 DSP Boosts Performance by Up to 10X for Automotive Radar/Lidar and Up to 30X for 5G Communications
- UltraSoC brings SEGGER J-Link to embedded debug and analytics environment
- Cadence Tensilica HiFi Audio DSP is the First DSP IP Core to Support Dolby Atmos for PCs
Breaking News
- Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
- Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution
- S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development
- PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
Most Popular
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- Cadence to Acquire Arm Artisan Foundation IP Business
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New Breakthroughs in China's RISC-V Chip Industry
- Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |