NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
Visit Quadric at CES to Discover the GPNPU that Solves The Biggest ML Inference Chip Design Challenges
Burlingame, CA – December 11, 2023 – Quadric® today announced that representatives from the company will be at the Consumer Electronics Show (CES) in Las Vegas, January 9-12, 2024. Email meetquadric@quadric.io to set up a meeting to learn how a general-purpose neural processing unit (GPNPU) solves the challenge of needing to artificially partition code between an NPU and a digital signal processor (DSP) and/or central processing unit (CPU).
“Because it’s fully programmable, our GPNPU runs all types of machine learning networks, including classical backbones, vision transformers, and large language models,” stated Steve Roddy, Quadric’s Chief Marketing Officer. “One architecture for ML inference plus pre-and-post processing greatly simplifies SoC hardware design and software programming. Porting new artificial intelligence (AI) and ML code is quick and efficient. No hardware changes are required, which means no silicon re-spins are required.”
Quadric’s processor architecture uniquely combines the best attributes of C++ programmability – the ability to run any ML model – with the performance efficiency of NPU accelerators found in many first-generation SoCs in the market today. But unlike inflexible accelerators that force silicon respins when complex new models such as Llama2 are invented, Chimera cores are fully programmable. Chimera GPNPUs run any model. All of the model – all of the layers. No removal of problematic layers. No partitioning. No forcing the data scientist to convert convolutions to adhere to the limited subset of conv types supported in hardware. Any model, any network, any operator.
About Quadric
Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms. Quadric’s unified hardware and software architecture is optimized for on-device ML inference. Learn more at www.quadric.io.
|
Related News
- Quadric Presents and Demos AI+ML Chimera GPNPU at Embedded Vision Summit 2024
- intoPIX Solutions Tackle the Biggest Challenges in Automotive Imaging at ADAS & Autonomous Vehicle Expo 2024
- Quadric's 3rd Generation Chimera GPNPU Product Family Expands to 864 TOPs, Adds Automotive-Grade Safety Enhanced Versions
- Quadric Announces Llama2 LLM Support Immediately Available for Chimera GPNPUs
- Quadric's DevStudio Speeds Software Development with Industry's First Integrated ML + DSP Cloud-Based Code Development Platform
Breaking News
- Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
- Xylon Introduces Xylon ISP Studio
- Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
- Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
Most Popular
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |