NVM OTP NeoBit in Vanguard (350nm, 250nm, 180nm, 160nm, 150nm, 110nm)
Certus releases radiation-hardened I/O Library in GlobalFoundries 12nm LP/LP+
January 29, 2025 -- Certus Semiconductor is pleased to announce that it has begun 2025 with the delivery of a radiation-hardened by design I/O library in GlobalFoundries 12nm LP/LP+ technology to a tier one customer. This design incorporates silicon-proven ESD that had been delivered previously to another tier one customer. The library includes a 1.8V and 3.3V GPIO with multiple drive strengths, along with a full-speed output enable function. The library includes an optional LDO to generate an internal reference for 3.3V Operation, as an alternative to an external 1.8V supply. The silicon-proven ESD cells have been proven up to 64MeV proton test and Heavy ION SEE (LET 85) Testing and are currently in production in a separate product line. A fail-safe GPI allows user to interface with bus-type protocols like GMII in a radiation environment. Certus is excited for this IP to go to production later this year! Please click here to learn more about Certus’ radiation-hardened and automotive-grade solutions!
|
Certus Semiconductor Hot IP
Related News
- Certus Semiconductor releases I/O library in TowerJazz's 65nm process
- Certus Semiconductor releases ESD library in GlobalFoundries 12nm Finfet process
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- OIF Releases Common Electrical I/O 5.0 Implementation Agreement
- BAE Systems collaborates with GlobalFoundries to produce radiation-hardened single board computers for space
Breaking News
- Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
- Xylon Introduces Xylon ISP Studio
- Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
- Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
Most Popular
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |