New Silicon IP
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Scalable, On-Die Voltage Regulation for High Current Applications
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40G UCIe PHY IP on Samsung SF4X
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
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PCIe 4.0 PHY on 5nm
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
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0.75V Power On Reset
- 4nm Low Power Plus (LN04LPP) CMOS device technology
- Single power supply: 0.675V to 0.825V
- Operational Junction Temperature(Tj): -40℃ to 125℃
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8.5GHz Fractional-N/SSC PLL
- 4nm Low Power Plus (LN04LPP) CMOS device technology
- Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
- Operating junction temperature(TJ): -40°C ~ 125°C
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1.8V general purpose I/O for 4nm FinFET
- Functional I/O circuit and ESD protection cells
- Enable higher voltage tolerance, beyond foundry I/O voltage levels
- Overvoltage tolerant design
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DDR5 PHY for Samsung SF4X
- Low latency, small area, low power
- Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
- Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
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LPDDR5X/5/4X PHY IP in SF5A for Automotive
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
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