Novelics’ coolSRAM-6T embedded memory IP is an ideal solution for ASIC, ASSP and System-on-Chip (SoC) applications with stringent power, speed or area requirements. Embedded coolSRAM-6T is designed to deliver the best performance and power characteristics at any given instance size. The coolSRAM-6T ...

Novelics’ coolSRAM-8T embedded memory IP is an ideal solution for ASIC, ASSP and System-on-Chip (SoC) applications with stringent power, speed or area requirements. Embedded coolSRAM-8T is designed to deliver the best performance and power characteristics at any given instance size. The coolSRAM-8T ...

Provides a SRAM design service customised to customer specification. SureFIT deploys silicon proven and patented low-power design techniques with powerful verification and characterization methodologies to deliver optimal memory solutions.

Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility ...

Comcores PCS IP core is a silicon agnostic implementation of the PCS layer compliant with Ethernet standard IEEE 802.3-2018. The IP-core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent ...

The JTAG <b><i>e</i></b>VC is a scalable and extensible tool built on top of Cadence’s industry leading Specman Elite [TM] platform, bringing best-in-class verification methodologies to test’s universal standard, with excellent reusability and return-on-investment. From developing a JTAG TAP ...

The MIPI SoundWire Verification IP (VIP) supports MIPI SoundWire specification version 0.4.

Mature and highly capable compliance verification solution. ncorporating the latest protocol updates, the mature and comprehensive Cadence^® Verification IP (VIP) for the Ethernet Base-T1 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. ...

Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface (CHI) specification, which is part of the Arm^® AMBA^® family of protocols. Incorporating the latest protocol updates, the Cadence^® Verification IP for AXI provides a complete ...

The Simulation VIP is ready-made for your environment, providing consistent results whether you are using Incisive®, Synopsys VCS®, or Mentor Questa® simulators. You have the freedom to build your testbench using any of these verification languages: SystemVerilog, e, Verilog, VHDL, or C/C++. ...

Aug. 31, 2023 - In this article, we will explore the concept of design verification, its importance, the process involved, the languages and methodologies used, and the future prospects of this critical phase in the development of VLSI design.

Aug. 22, 2022 - In this article, let me walk you through various verification methodologies we use for verifying IPs, Sub-systems, and SoCs and explain why we need new methodologies/standards like PSS.

Mar. 17, 2016 - The IoT sensor backplane is increasingly expected to monitor the system under test on a real-time basis. This is true for IoT sensor solutions monitoring body area networks, safety and security solutions, industrial factory and process automation solutions, and building automation solutions to name ...

Jun. 16, 2014 - IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, quality and maintainability of the translated code. VHDL and SystemC are frequently co-simulated by ...

Jun. 02, 2011 - ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a ...

Jun. 30, 2022 - Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the “TrekApps” family, today joined RISC-V International (RVI) as a strategic member.

Jun. 17, 2021 - Advantest Corporation is pilot testing a next-generation solution for performing both high-speed scan testing and software-driven functional device testing on the V93000 platform by leveraging the existing high-speed serial I/O interfaces on advanced integrated circuits (ICs).

Oct. 26, 2020 - Synopsys today announced that in collaboration with Samsung Foundry, more than 30 new interoperable process design kits (iPDKs) have been jointly developed, validated and support the Synopsys Custom Design Platform.

Jul. 05, 2016 - PLDA Training leverages PLDA’s industry expertise in IP Connectivity design to share best-in-class techniques on their customers’ own schedules to cost-effectively optimize their projects

May. 02, 2008 - Cadence Design Systems, Inc. today announced the immediate availability of multiple, silicon-ready RTL to GDSII implementation flows based on the Cadence® Encounter® digital IC design platform, for the ARM® Cortex™-A9 processor.

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