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Dilithium IP Core

• Supports sign and verify operations.
• Supports all three Dilithium modes.
• Has fully stallable input and output interfaces.

8-bit/12-bit JPEG Codec IP upto 64Kx64K

• Compliant with the Extended sequential DCT mode of ISO/IEC 10918-1 JPEG standard, the WAVEJ can also support motion JPEG streams with varied color formats supporting resolutions up to 64K x 64K.

112G Ethernet PHY IP LR-Max for TSMC N4P

• Includes one, two, four, eight or sixteen full-duplex transceivers (transmit and receive functions)

PCIe GEN6 PHY

• Supports PRBS (Pseudo Random Binary Sequence) testing including loopback modes

Post-Quantum Cryptography - PQC Key Encapsulation IP Core (ML-KEM)

• FIPS 203 compliant
• Supports ML-KEM 512/768/1024 sets
• Self-contained engine with a minimal attack surface

CC-7xx CryptoManager Core

• Main processor agnostic
• Standard secure applications
• Technology and process node independent

Dual Saturation Detector

• Power Supply: 1.8 V
• Input range (differential swing) : 200 mV to 500 mV
• Input common mode voltage : 1.045 V to 1.239 V

AV1/HEVC/AVC/VP9 Video Codec HW IP 8K30fps@550MHz

• High-quality encoding
• Improved bandwidth efficiency
• Low delay encoding

Low Noise, High PSRR Replica Voltage Regulator

• Power Supply : 1.8 V
• Output voltage : 1.2 V
• Quiescent current: 7.3 mA

LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X

• Complete, integrated LPDDR5X/5/4X solution from a single vendor when combined with Synopsys’ LPDDR5X/5/4X PHY IP

KYBER IP Core

• supports encapsulation and decapsulation operations
• supports all modes K=2,3,4.
• is compliant with Kyber specification round 3.

High-efficiency vector DSP cores for 5G and 5G-Advanced

• True dual-threaded hardware, including dual processing elements and dual instruction and data memory subsystems for contention-free multithread execution

LPDDR5 IP - High performance and low power

• Support LPDDR5 up to 6400Mbps
• Support Channel equalization with 1-tap DFE

TSMC FPD-Link / OpenLDI / LVDS forwarded clock SERDES Link

• Universal LVDS-based interfaces supporting variety of Tx and Rx configurations.

TSMC GF Intel Samsung Deskew Frequency Synthesizer PLL

SerDes Hard Macro-IP in GlobalFoundries 22FDX

• Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture

Smart Network-on-Chip (NoC) IP

• Smart NoC automation
• Topology generation with minimum wire length
• Scripting-driven regular topology creation

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

7-bit, 64 GSPS ADC Ultra Low Power

• Ultra-high bandwidth time-interleaved ADC
• 7-bit ADC resolution
• Sampling rate up to 64GSPS

1GHz to 3GHz, 6MHz to 100MHz Fractional-N Phase-Locked Loop

• TSMC SiGe BiCMOS 180nm
• Output clock frequency range from 6MHz to 100MHz
• Output LO frequency range from 1GHz to 3GHz

USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)

UCIe D2D Adapter

• Ultra Low Latency
• CRC and Retry, or Parity Computation
• Multiple Protocols,

CXL 3 Controller

• Supports configuration of PCIe vs CXL protocol mode
• Supports both RC and EP modes

Fully Configurable Radix 2 FFT/IFFT Processor