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DXTP GPU - Advanced graphics and compute acceleration for power constrained devices

• The ideal platform for edge compute
• Pixel-perfect graphics
• Everything developers need

MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL

• Supports MIPI Alliance Specification for C-PHY Version 2.1
• Consists of 3 Data lanes/trios
• Embedded, high performance, and highly programmable PLL

24-bit audio inductor-less class-D DAC with efficiency and ultra-low latency capability

• Provide a top-tier performances audio DAC to fabless and IC companies willing to integrate audio features directly in their product and not using external IC

Post-quantum secure root of trust subsystem

• Secure key management features
• Configurable power-side channel countermeasures.
• Configurable fault-tolerance countermeasures.

14-bit, 2.4 GSPS High Performance Swift™ DAC in 16nm CMOS

• 16nm CMOS
• 14-bit resolution
• 2.4GSPS update rate

1.8V & 3.3V Radiation Hardened GPIO with Optimized LDO

• 2mA, 4mA, 8mA and 16mA drive strengths
• Pairs with optimized LDO (3.3V only)
• Full-speed output enable

112G Ethernet PHY IP for TSMC N6

• Supports full-duplex 1.25 to 112Gbps data rates in 1, 2, and 4 lanes
• Enables 100G, 200G, 400G, 800G

7 μW always on Audio feature extraction with filter banks

• µW power consumption
• Integted Voice Activity Detection
• Running on a 32kHz clock in the always on domain

Cryogenic Contact Programmable ROM qualified down to 4K operating temperature

• Specially Engineered CryoCMOS IP
• Characterised down to 4°K
• Minimal Power Dissipation

Ultra Low Latency 100G MAC/PCS for edge AI supports Ultra Ethernet

• Ultra Low Latency
• Supports ULTRA Ethernet Standard

LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL

• TSMC 22 nm Logic Ultra Low Leakage Process
• Power Supply: 1.1V, 1.2V, 1.5V(dependent on DDR type), and 1.8V
• Metal Stack Option: 1P8M5X2Z with RDL

PCIe 5.0 PHY for TSMC N3P

• Physical Coding Sublayer (PCS) block with PIPE interface
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
• Lane margining at the receiver

DDR3/ 3L/ DDR4/ LPDDR4 PHY, TSMC 22nm ULP/ULL Technology

• Compliant with JEDEC DDR3, DDR3L DDR4 and LPDDR4 Standards
• Compliant with AMBA APB 3.0 for register accessing

UCIe and BOW Universal PHY

• Novel Redundancy for Hi-Rel,
• Support for 16&18-bit wide data,
• Support Synchronous Operation,

UCIE 2.0 Controller

• Compliant with UCIe 2.0 specification
• High bandwidth and low latency controller design

1.6T Ethernet UMAC

• Low latency, cut-through datapath.
• Simple programming and bringing up sequence matching previous UMAC generations.

Ultra Low Power Embedded SRAM on TSMC 16FFC

• Delivers both dynamic power savings and static power savings compared to industry standard SRAMs
• Ideal for replacing current SRAM IP and delivering SoC-wide power benefits

Multi-protocol SerDes PMA - PCIe1 PCIe2 PCIe3 PCIe4 PCIe5 and more

• Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
• Extremely low jitter suitable for Enterprise SerDes applications

12-bit, 9 GSPS High Performance Swift™ ADC in 16nm CMOS

• 16nm CMOS
• Ultra high-performance low-power ADC
• 12-bit ADC resolution

8.5GHz Fractional-N/SSC PLL

• 4nm Low Power Plus (LN04LPP) CMOS device technology
• Dual power supply of 1.2V±10% and 0.85V+5% ~ 0.75V-10%
• Operating junction temperature(Tj): -40°C ~ 125°C

HBM3 PHY IP for TSMC N4

• Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
• 16 independent 64-bit memory channels

TSMC CLN7FF 7nm Clock Generator PLL

• 800MHz-4000MHz
• Delivers optimal jitter performance over all multiplication settings.

3.3V to 2.5V 50mA LDO voltage regulator

• Samsung 28nm LPP
• 3.3V analog input voltage
• 1.0V digital input voltage

USB4 PHY in TSMC (N7, N6, N5, N4P, N3E, N3P)